ML1565 datasheet(20/21 Pages) MINILOGIC

20 / 21 page

P20/21

Rev. C, Sep 2005

ML1565

Applications Information (3)

Using SDOK for Power Sequencing

SDOK goes low when the step-down reaches regulation.

Some microcontrollers with low-voltage cores require that

the high-voltage (3.3V) I/O rail not be powered up until the

core has a valid supply. The circuit in Figure 11

accomplishes this by driving the gate of a PFET

connected

between

the

3.3V

output

and

the

microcontroller I/O supply. Alternately, power sequencing

may be implemented by connecting RC networks to the

appropriate converter ON_ inputs.

Figure 11. Using SDOK to Gate 3.3V Power to CPU

After the Core Voltage is OK

Setting OUTSD Below 1.25V

The step-down feedback voltage is 1.25V when FBSELSD

is high. With a standard two-resistor feedback network,

the output voltage may be set to values between 1.25V

and the input voltage. If a step-down output voltage less

than 1.25V is desired, it can be set by adding a third

feedback resistor from FB to a voltage higher than 1.25V

(the step-up output is a convenient voltage for this) as

shown in Figure 12. The equation governing output

voltage shown in Figure 12 is:

0= [(VSD – VFBSD) / R1] +[(0 – VFBSD) / R2]

+ [(VSU – VFBSD) / R3]

where VSD is the output voltage, VFBSD is 1.25V, and VSU is

the step-up output voltage. Note that any available voltage

that is higher than 1.25V can be used as the connection

point for R3 on Figure 12 and for the VSD term in the

equation. Since there are multiple solutions for R1, R2, and

R3, the above equation cannot be written in terms of one

resistor. The best method for determining resistor values is

to enter the above equation into a spreadsheet and test

estimated resistors’ values. A good starting point is with

100kΩ at R2 and R3.

Figure 12. Setting OUTSD for Outputs Below 1.25V

Designing a PC Board

Good PC board layout is important to achieve optimal

performance from the ML1565. Poor design can cause

excessive conducted and/or radiated noise.

Conductors carrying discontinuous currents, and any

high-current path should be made as short and wide as

possible. A separate low-noise ground plane containing the

reference and signal grounds should connect to the

power-ground plane at only one point to minimize the effect

of power-ground currents. Typically, the ground planes are

best joined right at the IC.

Keep the voltage feedback network very close to the IC,

preferably within 0.2in (5mm) of the FB_ pin. Nodes with

high dV/dt (switching nodes) should be kept as small as

possible and should be routed away from high-impedance

nodes such as FB_.

ML1565

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