56F8322 datasheet(33/136 Pages) FREESCALE

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Interrupt Vector Table

56F8322 Technical Data, Rev. 16

Freescale Semiconductor

Preliminary

Note: Program RAM is NOT available on the 56F8122 device.

4.3 Interrupt Vector Table

Table 4-3 provides the device’s reset and interrupt priority structure, including on-chip peripherals. The

table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table.

As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over

interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority

level, the lowest vector number has the highest priority.

The location of the vector table is determined by the Vector Base Address (VBA). Please see

Section 5.6.11 for the reset value of the VBA.

In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the

interrupt vector table. In these instances, the first two locations in the vector table must contain branch or

JMP instructions. All other entries must contain JSR instructions.

Note: PWM, CAN and Quadrature Decoder are NOT available on the 56F8122 device.

Table 4-2 Program Memory Map at Reset

Begin/End Address

Memory Allocation

P: $1F FFFF

P: $03 0000

RESERVED

P: $02 FFFF

P: $02 F800

On-Chip Program RAM

4KB

P: $02 F7FF

P: $02 1000

RESERVED

P: $02 0FFF

P: $02 0000

Boot Flash

8KB

Cop Reset Address = $02 0002

Boot Location = $02 0000

P: $01 FFFF

P: $00 4000

RESERVED

P: $00 3FFF

P: $00 0000

Internal Program Flash

32KB

Table 4-3 Interrupt Vector Table Contents1

Peripheral

Vector

Number

Priority

Level

Vector Base

Address +

Interrupt Function

Reserved for Reset Overlay2

Reserved for COP Reset Overlay2

core

P:$04

Illegal Instruction

core

P:$06

SW Interrupt 3

core

P:$08

HW Stack Overflow

core

P:$0A

Misaligned Long Word Access

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