56F8322 datasheet(43/136 Pages) FREESCALE

43 / 136 page

Peripheral Memory Mapped Registers

56F8322 Technical Data, Rev. 16

Freescale Semiconductor

Preliminary

Table 4-11 Quadrature Decoder 0 Registers Address Map

(DEC0_BASE = $00 F180)

Quadrature Decoder is NOT available in the 56F8122 device

Address Offset

DEC0_DECCR

Decoder Control Register

DEC0_FIR

Filter Interval Register

DEC0_WTR

Watchdog Time-out Register

DEC0_POSD

Position Difference Counter Register

DEC0_POSDH

Position Difference Counter Hold Register

DEC0_REV

Revolution Counter Register

DEC0_REVH

Revolution Hold Register

DEC0_UPOS

Upper Position Counter Register

DEC0_LPOS

Lower Position Counter Register

DEC0_UPOSH

Upper Position Hold Register

DEC0_LPOSH

Lower Position Hold Register

DEC0_UIR

Upper Initialization Register

DEC0_LIR

Lower Initialization Register

DEC0_IMR

Input Monitor Register

Table 4-12 Interrupt Control Registers Address Map

(ITCN_BASE = $00 F1A0)

Address Offset

IPR0

Interrupt Priority Register 0

IPR1

Interrupt Priority Register 1

IPR2

Interrupt Priority Register 2

IPR3

Interrupt Priority Register 3

IPR4

Interrupt Priority Register 4

IPR5

Interrupt Priority Register 5

IPR6

Interrupt Priority Register 6

IPR7

Interrupt Priority Register 7

IPR8

Interrupt Priority Register 8

IPR9

Interrupt Priority Register 9

VBA

Vector Base Address Register

FIM0

Fast Interrupt Match Register 0

FIVAL0

Fast Interrupt Vector Address Low 0 Register

FIVAH0

Fast Interrupt Vector Address High 0 Register

FIM1

Fast Interrupt Match Register 1

FIVAL1

Fast Interrupt Vector Address Low 1 Register

FIVAH1

$10

Fast Interrupt Vector Address High 1 Register

56F8322 Datasheet(PDF) 43 Page - Freescale Semiconductor, Inc

56F8322 Datasheet(HTML) 43 Page - Freescale Semiconductor, Inc

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