Analog Integrated Circuit Device Data

Freescale Semiconductor

7

33996

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions of 3.1 V

≤ SO

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING (VPWR)

Output Slew Rate

(15)

SR

1.0

2.0

10

V/

µs

Output Turn ON Delay Time (16)

1.0

2.0

10

µs

Output Turn OFF Delay Time (16)

1.0

4.0

10

µs

Output ON Short Fault Disable Report Delay (17)

100

–

450

µs

Output OFF Open Fault Delay Time (17)

100

–

450

µs

Output PWM Frequency

–

–

2.0

kHz

DIGITAL INTERFACE TIMING (CS, SO, SI, SCLK) (23)

(18)

–

–

10

µs

Falling Edge of CS to Rising Edge of SCLK

Required Setup Time

100

–

–

ns

Falling Edge of SCLK to Rising Edge of CS

Required Setup Time

50

–

–

ns

SI to Falling Edge of SCLK

Required Setup Time

16

–

–

ns

Falling Edge of SCLK to SI

Required Hold Time

20

–

–

ns

SI, CS, SCLK Signal Rise Time (19)

–

5.0

–

ns

SI, CS, SCLK Signal Fall Time (19)

–

5.0

–

ns

Time from Falling Edge of CS to SO Low Impedance (20)

–

–

50

ns

Time from Rising Edge of CS to SO High Impedance (21)

–

–

50

ns

Time from Rising Edge of SCLK to SO Data Valid (22)

–

25

80

ns

Notes

15.

Output slew rate measured across a 60

Ω resistive load.

16.

Output turn ON and OFF delay time measured from 50% rising edge of CS to 80% and 20% of initial voltage.

17.

Duration of fault before fault bit is set. Duration between access times must be greater than 450

µs to read faults.

18.

This parameter is guaranteed by design; however, it is not production tested.

19.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

20.

Time required for valid output status data to be available on SO pin.

21.

Time required for output states data to be terminated at SO pin.

22.

Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.

23.

This parameter is guaranteed by design. Production test equipment used 4.16 MHz, 5.5 V/3.1 V SPI Interface.