ADS9813 datasheet(39/57 Pages) TI1

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7.2.6 Register 18h (offset = 18h) [reset = 0h]

Figure 7-25. Register 18h

RESERVED

R/W-0h

RAMP_INC_B

TP_MODE_B

TP_EN_B

RESERVED

R/W-0h

Figure 7-26. Register 18h Field Descriptions

Bit

Field

Type

Reset

Description

15-8

RESERVED

R/W

Reserved. Do not change from the default reset value.

7-4

RAMP_INC_B

R/W

Increment value for the ramp pattern output. The output

ramp increments by N+1, where N is the value configured

in this register.

3-2

TP_MODE_B

R/W

Select digital test pattern for analog input channels 5, 6, 7,

and 8.

0 : Fixed pattern from the TP0_B register

1 : Fixed pattern from the TP0_B register

2 : Digital ramp output

3 : Alternate fixed pattern output from the TP0_B and

TP1_B registers

TP_EN_B

R/W

Enable digital test pattern for data corresponding to

channels 5, 6, 7, and 8.

0 : Data output is the ADC conversion result

1 : Data output is the digital test pattern

RESERVED

R/W

Reserved. Do not change from the default reset value.

7.2.7 Register 19h (offset = 19h) [reset = 0h]

Figure 7-27. Register 19h

TP0_B[15:0]

R/W-0h

TP0_B[15:0]

R/W-0h

Figure 7-28. Register 19h Field Descriptions

Bit

Field

Type

Reset

Description

15-0

TP0_B[15:0]

R/W

Lower 16 bits of test pattern 0

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ADS9813

SBASAQ6 – APRIL 2024

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