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ADS9813 Datasheet(PDF) 11 Page - Texas Instruments |
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ADS9813 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 57 page ![]() 5.7 Switching Characteristics at AVDD_5V = 4.75V to 5.25V, VDD_1V8 = 1.75V to 1.85V, IOVDD = 1.15V to 1.85V, VREF = 4.096V (internal or external), and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C PARAMETER TEST CONDITIONS MIN MAX UNIT RESET tPU Power-up time for device 25 ms SPI INTERFACE TIMINGS (Configuration Interface) tden_CKDO Delay time: 8th SCLK rising edge to data enable 22 ns tdz_CKDO Delay time: 24th SCLK rising edge to SDO going Hi-Z 50 ns td_CKDO Delay time: SCLK falling edge to corresponding data valid on SDO 16 ns tht_CKDO Delay time: SCLK falling edge to previous data valid on SDO 2 ns CMOS DATA INTERFACE tDCLK Data clock output DDR mode 10 ns SDR mode 20 Clock duty cycle 45 55 % toff_DCLKDO_r Time offset: DCLK rising to corresponding data valid DDR mode tDCLK / 4 – 1.5 tDCLK / 4 + 1.5 ns toff_DCLKDO_f Time offset: DCLK falling to corresponding data valid DDR mode tDCLK / 4 – 1.5 tDCLK / 4 + 1.5 ns td_DCLKDO Time delay: DCLK rising to corresponding data valid SDR mode –1 1 ns td_SYNC_FCLK Time delay: SMPL_CLK falling edge with SYNC signal to corresponding FCLKOUT rising edge 3 4 tSMPL_CLK 5.8 Timing Diagrams CS SCLK SDI SDO A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 tsu_CKDI tht_CKDI td_CKDO tht_SDO td_CSCK thi_CS SDO is active only when reading registers; Hi-Z otherwise tdz_CKDO DO 15 DO 14 DO 13 DO 12 DO 11 DO 10 DO 9 DO 8 DO 7 DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0 td_CKCS Hi-Z tden_CKDO 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 5-1. SPI Configuration Interface www.ti.com ADS9813 SBASAQ6 – APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: ADS9813 |
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