AD7785

Rev. 0 | Page 14 of 32

ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip

registers, which are described on the following pages. In the

following descriptions, set implies a Logic 1 state and cleared

implies a Logic 0 state, unless otherwise stated.

COMMUNICATIONS REGISTER

RS2, RS1, RS0 = 0, 0, 0

The communications register is an 8-bit write-only register. All

communications to the part must start with a write operation to

the communications register. The data written to the communi-

cations register determines whether the next operation is a read

or write operation, and to which register this operation takes

place. For read or write operations, once the subsequent read or

write operation to the selected register is complete, the interface

returns to where it expects a write operation to the communica-

tions register. This is the default state of the interface and,

on power-up or after a reset, the ADC is in this default state

waiting for a write operation to the communications register. In

situations where the interface sequence is lost, a write operation

of at least 32 serial clock cycles with DIN high returns the ADC

to this default state by resetting the entire part. Table 9 outlines

the bit designations for the communications register. CR0

through CR7 indicate the bit location, CR denoting the bits are

in the communications register. CR7 denotes the first bit of the

data stream. The number in parentheses indicates the power-

on/reset default status of that bit.

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

WEN(0)

R/W(0)

RS2(0)

RS1(0)

RS0(0)

CREAD(0)

0(0)

0(0)

Table 9. Communications Register Bit Designations

Bit Location

Bit Name

Description

CR7

WEN

Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually

occurs. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this

bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits are loaded to

the communications register.

CR6

R/W

A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position

indicates that the next operation is a read from the designated register.

CR5 to CR3

RS2 to RS0

Register Address Bits. These address bits are used to select which of the ADC’s registers are being selected

during this serial interface communication. See Table 10.

CR2

CREAD

Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial

interface is configured so that the data register can be continuously read. For example, the contents of the

data register are placed on the DOUT pin automatically when the SCLK pulses are applied after the RDY pin

goes low to indicate that a conversion is complete. The communications register does not have to be written

to for data reads. To enable continuous read mode, the instruction 01011100 must be written to the

communications register. To exit the continuous read mode, the instruction 01011000 must be written to the

communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity

on the DIN line so that it can receive the instruction to exit continuous read mode. Additionally, a reset occurs

if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an

instruction is to be written to the device.

CR1 to CR0

0

These bits must be programmed to Logic 0 for correct operation.

Table 10. Register Selection

RS2

RS1

RS0

Register

Register Size

0

0

0

Communications Register During a Write Operation

8-bit

0

0

0

Status Register During a Read Operation

8-bit

0

0

1

Mode Register

16-bit

0

1

0

Configuration Register

16-bit

0

1

1

Data Register

24-bit (20-bit conversion followed by four 1s)

1

0

0

ID Register

8-bit

1

0

1

IO Register

8-bit

1

1

0

Offset Register

24-bit

1

1

1

Full-Scale Register

24-bit