M68HC05 datasheet(48/118 Pages) FREESCALE

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Input/Output (I/O) Ports

MC68HC05C9A Advance Information Data Sheet, Rev. 4.1

Freescale Semiconductor

7.3 Port B

Port B is an 8-bit bidirectional port. The port B data register is at $0001 and the data direction register

(DDR) is at $0005. The contents of the port B data register are indeterminate at initial powerup and must

be initialized by user software. Reset does not affect the data registers, but clears the data direction

registers, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port pin to

output mode. Each of the port B pins has an optional external interrupt capability that can be enabled by

programming the corresponding bit in the port B mask option register ($3FF0).

The interrupt option also enables a pullup device when the pin is configured as an input. The edge or

edge- and level-sensitivity of the IRQ pin will also pertain to the enabled port B pins. Care needs to be

taken when using port B pins that have the pullup enabled. Before switching from an output to an input,

the data should be preconditioned to a 1 to prevent an interrupt from occurring. The port B logic is shown

in Figure 7-2.

7.4 Port C

Port C is an 8-bit bidirectional port. The port C data register is at $0002 and the data direction register

(DDR) is at $0006. The contents of the port C data register are indeterminate at initial powerup and must

be initialized by user software. Reset does not affect the data registers, but clears the data direction

registers, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to

output mode. PC7 has a high current sink and source capability. Figure 7-1 is also applicable to port C.

7.5 Port D

When configured as a C9A, port D is a 7-bit bidirectional port; when configured as a C12A, port D is a

7-bit fixed input port. Four of its pins are shared with the SPI subsystem and two more are shared with

the SCI subsystem. The contents of the port D data register are indeterminate at initial powerup and must

be initialized by user software. During reset all seven bits become valid input ports because the C9A DDR

bits are cleared and the special function output drivers associated with the SCI and SPI subsystems are

disabled, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to

output mode only when configured as a C9A.

M68HC05 Datasheet(PDF) 48 Page - Freescale Semiconductor, Inc