M68HC05 datasheet(61/118 Pages) FREESCALE

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Functional Description

MC68HC05C9A Advance Information Data Sheet, Rev. 4.1

Freescale Semiconductor

9.5 Functional Description

A block diagram of the SCI is shown in Figure 9-1. Option bits in serial control register1 (SCCR1) select

the wakeup method (WAKE bit) and data word length (M bit) of the SCI. SCCR2 provides control bits that

individually enable the transmitter and receiver, enable system interrupts, and provide the wakeup enable

bit (RWU) and the send break code bit (SBK). Control bits in the baud rate register (BAUD) allow the user

to select one of 32 different baud rates for the transmitter and receiver.

Data transmission is initiated by writing to the serial communications data register (SCDR). Provided the

transmitter is enabled, data stored in the SCDR is transferred to the transmit data shift register. This

transfer of data sets the transmit data register empty flag (TDRE) in the SCI status register (SCSR) and

generates an interrupt (if transmitter interrupts are enabled). The transfer of data to the transmit data shift

first. Upon completion of data transmission, the transmission complete flag (TC) in the SCSR is set

(provided no pending data, preamble, or break is to be sent) and an interrupt is generated (if the transmit

complete interrupt is enabled). If the transmitter is disabled, and the data, preamble, or break (in the

transmit data shift register) has been sent, the TC bit will be set also. This will also generate an interrupt

if the transmission complete interrupt enable bit (TCIE) is set. If the transmitter is disabled during a

transmission, the character being transmitted will be completed before the transmitter gives up control of

the TDO pin.

When SCDR is read, it contains the last data byte received, provided that the receiver is enabled. The

receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has been

transferred from the input serial shift register to the SCDR; this will cause an interrupt if the receiver

interrupt is enabled. The data transfer from the input serial shift register to the SCDR is synchronized by

the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error flags in the SCSR may be

set if data reception errors occurred.

An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects idle

line transmission) in SCSR is set. This allows a receiver that is not in the wakeup mode to detect the end

of a message, or the preamble of a new message, or to re-synchronize with the transmitter. A valid

character must be received before the idle line condition or the IDLE bit will not be set and idle line

interrupt will not be generated.

Figure 9-2. Rate Generator Division

OSC FREQ

(fOSC)

÷2

BUS FREQ

(fOP)

SCP0–SCP1

SCI PRESCALER

SELECT

SCR0–SCR2

SCI RATE

SELECT

÷16

SCI TRANS

CLOCK (TX)

SCI RECEIVE

CLOCK (RT)

CONTROL

M68HC05 Datasheet(PDF) 61 Page - Freescale Semiconductor, Inc

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