M68HC05 datasheet(83/118 Pages) FREESCALE

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Instruction Types

MC68HC05C9A Advance Information Data Sheet, Rev. 4.1

Freescale Semiconductor

11.3.3 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The

unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register

operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter

when a test condition is met. If the test condition is not met, the branch is not performed.

The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first

256 memory locations. These 3-byte instructions use a combination of direct addressing and relative

addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte

is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the

program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of

the opcode. The span of branching is from –128 to +127 from the address of the next location after the

branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code

Table 11-3. Jump and Branch Instructions

Instruction

Mnemonic

Branch if Carry Bit Clear

BCC

Branch if Carry Bit Set

BCS

Branch if Equal

BEQ

Branch if Half-Carry Bit Clear

BHCC

Branch if Half-Carry Bit Set

BHCS

Branch if Higher

BHI

Branch if Higher or Same

BHS

Branch if IRQ Pin High

BIH

Branch if IRQ Pin Low

BIL

Branch if Lower

BLO

Branch if Lower or Same

BLS

Branch if Interrupt Mask Clear

BMC

Branch if Minus

BMI

Branch if Interrupt Mask Set

BMS

Branch if Not Equal

BNE

Branch if Plus

BPL

Branch Always

BRA

Branch if Bit Clear

BRCLR

Branch Never

BRN

Branch if Bit Set

BRSET

Branch to Subroutine

BSR

Unconditional Jump

JMP

Jump to Subroutine

JSR

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