M68HC05 datasheet(69/118 Pages) FREESCALE

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SCI I/O Registers

MC68HC05C9A Advance Information Data Sheet, Rev. 4.1

Freescale Semiconductor

FE — Receiver Framing Error Flag

This clearable, read-only flag is set when there is a logic 0 where a stop bit should be in the character

shifted into the receive shift register. If the received word causes both a framing error and an overrun

error, the OR flag is set and the FE flag is not set. Clear the FE bit by reading the SCSR and then

reading the SCDR.

1 = Framing error

0 = No framing error

9.13.5 Baud Rate Register

The baud rate register (BAUD), shown in Figure 9-12, selects the baud rate for both the receiver and the

transmitter.

SCP1 — SCP0–SCI Prescaler Select Bits

These read/write bits control prescaling of the baud rate generator clock, as shown in Table 9-1. Reset

clears both SCP1 and SCP0.

SCR2 — SCR0–SCI Baud Rate Select Bits

These read/write bits select the SCI baud rate, as shown in Table 9-2. Resets have no effect on the

SCR2–SCR0 bits.

$000D

Bit 7

6543

Bit 0

Read:

SCP1

SCP0

SCR2

SCR1

SCR0

Write:

Reset:

—

= Unimplemented

U = Undetermined

Figure 9-12. Baud Rate Register (BAUD)

Table 9-1. Baud Rate Generator Clock Prescaling

SCP[1:0]

Baud Rate Generator Clock

Internal Clock

÷ 1

Internal Clock

÷ 3

Internal Clock

÷ 4

Internal Clock

÷ 13

Table 9-2. Baud Rate Selection

SCR[2:0]

SCI Baud Rate (Baud)

000

Prescaled Clock

÷ 1

001

Prescaled Clock

÷ 2

010

Prescaled Clock

÷ 4

011

Prescaled Clock

÷ 8

100

Prescaled Clock

÷ 16

101

Prescaled Clock

÷ 32

110

Prescaled Clock

÷ 64

111

Prescaled Clock

÷ 128

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