M68HC05 datasheet(17/118 Pages) FREESCALE

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Mask Options

MC68HC05C9A Advance Information Data Sheet, Rev. 4.1

Freescale Semiconductor

C12A — C12A/C9A Mode Select Bit

This read/write bit selects between C12A configuration and C9A configuration.

1 = Configured to emulate MC68HC05C12A

0 = Configured to emulate MC68HC05C9A

C12IRQ — C12A Interrupt Request Bit

This read/write bit selects between an edge-triggered only or edge- and level-triggered external

interrupt pin. If configured in C9A mode, this bit has no effect and will be forced to 0 regardless of the

programmed state.

1 = Edge and level interrupt option selected

0 = Edge-only interrupt option selected

NOTE

Any Port B pin configured for interrupt capability will follow the same edge

or edge/level trigger as the IRQ pin.

STOPDIS — STOP Instruction Disable Bit

This read-only bit allows emulation of the “STOP disable” mask option on the MC68HC05C12A. (See

5.9 COP During Stop Mode.) If configured in MC68HC05C9A mode, this bit has no effect and will be

forced to 0 regardless of the programmed state.

1 = If the MCU enters stop mode, the clock monitor is enabled to force a system reset

0 = STOP instruction executed as normal

C12COPE — C12A COP Enable Bit

This read-only bit enables the COP function when configured in MC68HC05C12A mode. If configured

in MC68HC05C9A mode, this bit has no effect and will be forced to 0 regardless of the programmed

state.

1 = When in C12A mode, this enables the C12ACOP watchdog timer.

0 = When in C12A mode, this disables the C12ACOP watchdog timer.

SEC — Security Enable Bit

This read-only bit enables the EPROM security feature. Once programmed, this bit helps to prevent

external access to the programmed EPROM data. The EPROM data cannot be verified or modified.

1 = Security enabled

0 = Security disabled

NOTE

During power-on reset, the device always will be configured as

MC68HC05C9A regardless of the state of the C12A bit.

$3FF1

Bit 7

Bit 0

Read:

SEC

C12COPE

STOPDIS

C12IRQ

C12A

Write:

= Unimplemented

Figure 1-3. Mask Option Register 2

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