56F8036 datasheet(73/164 Pages) FREESCALE

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56F8036 Data Sheet, Rev. 3

Freescale Semiconductor

Preliminary

5.6.8.2

Vector Address Bus (VAB) Bits 13–0

The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower 7 bits

are determined based on the highest priority interrupt and are then appended onto VBA before presenting

the full VAB to the Core.

5.6.9

Fast Interrupt Match 0 Register (FIM0)

Figure 5-11 Fast Interrupt Match 0 Register (FIM0)

5.6.9.1

Reserved—Bits 15–6

This bit field is reserved. Each bit must be set to 0.

5.6.9.2

Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 5–0

These values determine which IRQ will be Fast Interrupt 0. Fast Interrupts vector directly to a service

routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table

first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast

Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority

level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt.

Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to

the vector table.

5.6.10 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

Figure 5-12 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

5.6.10.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0

The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0

to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

Base + $8

Read

FAST INTERRUPT 0

Write

RESET

00000

0000000

0000

Base + $9

Read

FAST INTERRUPT 0 VECTOR ADDRESS LOW

Write

RESET

00000

0000000

0000

56F8036 Datasheet(PDF) 73 Page - Freescale Semiconductor, Inc

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