PART NUMBER

UPB1007K

PACKAGE OUTLINE

QFN-36

SYMBOLS

PARAMETERS AND CONDITIONS

UNITS

MIN

TYP

MAX

Total Circuit Current, No Signals

mA

25

31

Supply Voltage

V

2.7

3.0

3.3

Ω)

Ω)

Ω)

Ω)

RF Input Impedance of LNA

Ω

28 - j38

RF Output Impedance of LNA

Ω

85 - jx6

1 dB Compression, Input matched

dBm

-22

dB

14

15

Noise Figure of LNA, Input matched

dB

2.8

3.2

Ω

Ω

Ω

Ω)

RF Input Impedance of Mixer

Ω

31 -j103

1 dB Compression (refer to input), Input matched

dBm

-25

Power Conversion Gain

dB

21

Noise Figure of Mixer (SSB), Input matched

dB

9.5

10

dBm

-40

dBm

-48

RF Output Impedance of Mixer

+152 - j9

PLL

1

-1

Phase Comparison Frequency

MHz

8.184

dB

12

dB

47

Gain Control Voltage (Voltage at maximum gain)

V

0.5

dB

20

(Voltage at maximum gain)

dB

-70

dB

-70

FEATURES

UPB1007K

3 V DUAL DOWNCONVERTER AND

PLL FREQUENCY SYNTHESIZER

DESCRIPTION

NEC's UPB1007K is a Silicon RFIC designed for low cost GPS

receivers. The IC combines an LNA, followed by a double-

conversion RF/IF downconverter block and a PLL frequency

synthesizer on one chip. The chip also includes an on-board

crystal oscillator working up to 16 MHz which can be used as

a CPU reference for fast locking. The device operates on a 3

V supply voltage and is housed in a small 36 pin QFN (Quad

Flat No-lead) package, resulting in low power consumption

and reduced board space. The device is manufactured using

NEC's stringent quality assurance and test procedures en-

sure the highest reliability and performance.

APPLICATIONS

• LOW POWER HANDHELD GPS RECEIVER

• IN-VEHICLE NAVIGATION SYSTEMS

• PC/PDA+GPS INTEGRATION

• INTEGRATED RF BLOCK:

LNA, RF & IF Downconverter + PLL frequency

synthesizer + on-chip crystal oscillator

PROCESS

• ADJUSTABLE GAIN: 20 dB range MIN

• FIXED DIVISION PRESCALER

• LOW POWER CONSUMPTION: 25 mA @ 3 V

• SMALL 36 PIN QFN PACKAGE

Flat lead style for better performance

• TAPE AND REEL PACKAGING AVAILABLE

California Eastern Laboratories