Philips Semiconductors

Product specification

SCN68562

Dual universal serial communications controller (DUSCC)

1995 May 01

9

NO.

UNIT

LIMITS

PARAMETER

FIGURE

NO.

UNIT

Max

Typ

Min

PARAMETER

FIGURE

42

16

CSN Low to transmit DMA REQ negated

400

nS

43

16

CSN Low to receive DONEN Low

300

nS

44

16

CSN Low to receive DMA REQ negated

400

nS

NOTES:

1. Parameters are valid over specified temperature range.

2. All voltage measurements are referenced to ground (GND). For DC and functional testing, all inputs except X1/CLK swing between 0.8V and

2.0V with a transition time of 20ns maximum. For X1/CLK, this swing is between 0.4V and 2.4V All time measurements are referenced at

input voltages of 0.4V and 2.4V for all inputs. Output levels are referenced at 1.2V and 2.0V, as appropriate.

4. This specification will impose maximum 68000 CPU CLK to 6MHz. Higher CPU CLK can be used if repeating bus cycles are not performed.

5. Execution of the valid command (after it is latched) requires three falling edges of X1 (see Figure 14).

6. In single address DMA mode write operation, data is latched by the falling edge of DTCN.

7. These values were not explicitly tested, they are guaranteed by design and characterization data.

8. These timings are from the falling edge of DTACKN (not CSN rising).

9. X1/CLK frequency must be at least four times the receiver serial data rate.

1

RESETN

SD00224

Figure 3. Reset Timing

A1–A6

R/WN

CSN

D0–D7

DTACKN

2

3

5

4

6

8

9

11

7

12

13

14

SD00225

Figure 4. Bus Timing (Read Cycle)

X1/CLK

DTACKN

COMMAND

VALID

SD00226

Figure 5. Command Timing