SCN68562 datasheet(3/18 Pages) PHILIPS

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Philips Semiconductors

Product specification

SCN68562

Dual universal serial communications controller (DUSCC)

1995 May 01

• 0 to 4MHz data rate

• Programmable bit rate for each receiver and transmitter selectable

from:

– 16 fixed rates: 50 to 38.4k baud

– One user-defined rate derived from programmable

counter/timer

– External 1X or 16X clock

– Digital phase-locked loop

• Parity and FCS (frame check sequence LRC or CRC) generation

and checking

• Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,

Manchester

• Programmable channel mode: full- and half-duplex, auto-echo, or

local loopback

• Programmable data transfer mode: polled, interrupt, DMA, wait

• DMA interface

– Compatible with the Philips Semiconductors SCB68430 Direct

Memory Access Interface (DMAI) and other DMA controllers

– Single- or dual-address dual transfers

– Half- or full-duplex operation

– Automatic frame termination on counter/timer terminal count or

DMA DONE

• Interrupt capabilities

– Daisy chain option

– Vector output (fixed or modified by status)

– Programmable internal priorities

– Maskable interrupt conditions

• Multi-function programmable 16-bit counter/timer

– Bit rate generator

– Event counter

– Count received or transmitted characters

– Delay generator

– Automatic bit length measurement

• Modem controls

– RTS, CTS, DCD, and up to four general I/O pins per channel

– CTS and DCD programmable autoenables for Tx and Rx

– Programmable interrupt on change of CTS or DCD

• On-chip oscillator for crystal

• TTL compatible

• Single +5V power supply

Asynchronous Mode Features

• Character length: 5 to 8 bits

• Odd or even parity, no parity, or force parity

• Up to two stop bits programmable in 1/16-bit increments

• 1X or 16X Rx and Tx clock factors

• Parity, overrun, and framing error detection

• False start bit detection

• Start bit search 1/2-bit time after framing error detection

• Break generation with handshake for counting break characters

• Detection of start and end of received break

• Character compare with optional interrupt on match

• Transmits up to 4Mbs and receive up to 2Mbps data rates

Character-Oriented Protocol Features

• Character length: 5 to 8 bits

• Odd or even parity, no parity, or force parity

• LRC or CRC generation and checking

• Optional opening PAD transmission

• One or two SYN characters

• External sync capability

• SYN detection and optional stripping

• SYN or MARK line-fill on underrun

• Idle in MARK or SYNs

• Parity, FCS, overrun, and underrun error detection

BISYNC Features

– EBCDIC or ASCII header, text and control messages

– SYN, DLE stripping

– EOM (end of message) detection and transmission

– Auto transparent mode switching

– Auto hunt after receipt of EOM sequence (with closing PAD

check after EOT or NAK)

– Control character sequence detection for both transparent and

normal text

Bit-Oriented Protocol Features

• Character length: 5 to 8 bits

• Detection and transmission of residual character: 0–7 bits

• Automatic switch to programmed character length for 1 field

• Zero insertion and deletion

• Optional opening PAD transmission

• Detection and generation of FLAG, ABORT, and IDLE bit patterns

• Detection and generation of shared (single) FLAG between

frames

• Detection of overlapping (shared zero) FLAGs

• ABORT, ABORT-FLAGs, or FCS FLAGs line-fill on underrun

• Idle in MARK or FLAGs

• Secondary address recognition including group and global

address

• Single- or dual-octet secondary address

• Extended address and control fields

• Short frame rejection for receiver

• Detection and notification of received end of message

• CRC generation and checking

• SDLC loop mode capability

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