Philips Semiconductors

Product specification

SCN68562

Dual universal serial communications controller (DUSCC)

2

1995 May 01

853-0831 15179

DESCRIPTION

The Philips Semiconductors SCN68562 Dual Universal Serial

Communications Controller (DUSCC) is a single-chip MOS-LSI

communications device that provides two independent,

multi-protocol, full-duplex receiver/transmitter channels in a single

package. It supports bit-oriented and character-oriented (byte count

and byte control) synchronous data link controls as well as

asynchronous protocols. The SCN68562 interfaces to the 68000

MPUs via asynchronous bus control signals and is capable of

program-polled, interrupt driven, block-move or DMA data transfers.

The operating mode and data format of each channel can be

programmed independently.

Each channel consists of a receiver, a transmitter, a 16-bit

multifunction counter/timer, a digital phase-locked loop (DPLL), a

parity/CRC generator and checker, and associated control circuits.

The two channels share a common bit rate generator (BRG),

operating directly from a crystal or an external clock, which provides

16 common bit rates simultaneously. The operating rate for the

receiver and transmitter of each channel can be independently

selected from the BRG, the DPLL, the counter/timer, or from an

external 1X or 16X clock, making the DUSCC well suited for

dual-speed channel applications. Data rates up to 4Mbits per

second are supported.

The transmitter and receiver each contain a four-deep FIFO with

appended transmitter command and receiver status bits and a shift

register. This permits reading and writing of up to four characters at

a time, minimizing the potential of receiver overrun or transmitter

underrun, and reducing interrupt or DMA overhead. In addition, a

flow control capability is provided to disable a remote transmitter

when the FIFO of the local receiving device is full.

Two modem control inputs (DCD and CTS) and three modem

control outputs are provided. These inputs and outputs can be

optionally programmed for other functions.

FEATURES

General Features

transmitter

– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,

etc.

– COP: BISYNC, DDCMP

– ASYNC: 5–8 bits plus optional parity

PIN CONFIGURATIONS

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

28

27

26

25

21

22

23

24

IACKN

A3

A2

A1

RTxDAKBN/

IRQN

RESETN

RTSBN/

TRxCB

RTxCB

DCDBN/

TxDAKBN/

RTxDRQBN/

TxDRQBN/

CTSBN/LCBN

D7

D6

D5

D4

DTACKN

DTCN

GND

CSN

DONEN

D3

D2

D1

D0

CTSAN/LCAN

TxDRQAN/

RTxDRQAN/

TxDAKAN/

TxDA

DCDAN/

RTxCA

TRxCA

RTSAN/

X2/IDCN

X1/CLK

RTxDAKAN/

A6

A5

A4

VDD

N PACKAGE

GPI1BN

SYNOUTBN

SYNIBN

RxDB

TxDB

GPI2BN

GPO1BN

GPO2BN/RTSBN

R/WN

GPO2AN/RTSAN

GPO1AN

GPI2AN

Rxda

SYNIAN

SYNOUTAN

GPI1AN

DIP

Pin Function

Pin Function

1

IACKN

27 CSN

2

A3

28 R/WN

3

A2

29 DONEN

4A1

30 D3

5

RTxDAKBN/

31 D2

GPI1BN

32 D1

6

IRQN

33 D0

7NC

34 NC

8

RESETN

35 CTSAN/LCAN

9

RTSBN/

36 TxDRQAN/

SYNOUTBN

GPO2AN/RTSAN

10 TRxCB

37 RTxDRQAN/

11

RTxCB

GPO1AN

12 DCDBN/

38 TxDAKAN/

SYNIBN

GPI2AN

13 NC

39 TxDA

14 RxDB

40 RxDA

15 TxDB

41 NC

16 TxDAKBN/

42 DCDAN/

GPI2BN

SYNIAN

17 RTxDRQBN/

43 RTxCA

GPO1BN

44 TRxCA

18 TxDRQBN/

45 RTSAN/

GPO2BN/RTSBN

SYNOUTAN

19 CTSBN/LCBN

46 X2/IDCN

20 D7

47 X1/CLK

21 D6

48 RTxDAKAN/

22 D5

GPI1AN

23 D4

49 A6

24 DTACKN

50 A5

25 DTCN

51 A4

26 GND

52 VDD

1

46

20

33

47

34

21

8

PLCC

7

TOP VIEW

INDEX

CORNER

A PACKAGE

SD00222

Figure 1. Pin Configurations