MAX96752 datasheet(32/159 Pages) AD

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flexible way. Bandwidth allocation is dynamic so that if a certain channel is not active, it does not consume any link

bandwidth, and all the remaining active channels can share the full link bandwidth. Maximum packet size is limited to

prevent a single channel from utilizing the link bandwidth for an extended time. In most cases, available link bandwidth

exceeds the bandwidth requirement. Idle packets are used to fill in the unused link bandwidth.

The same data protocol is used on forward and reverse channels and for both video and control-channel data.

GMSL2 Physical Layer

Analog Devices' GMSL2 family of serial links have transmitter and receiver capability enabled simultaneously, allowing

full-duplex operation on a single wire. A single cable between the serializer and deserializer delivers data being

transmitted from each end of the link. Forward transmission is data being sent from the serializer to the deserializer.

Reverse transmission is data being sent from the deserializer to the serializer.

Forward rate options are fixed at 3Gbps or 6Gbps, with defaults of 6Gbps in Coax mode and 3Gbps in STP mode. The

reverse rate is fixed at 187.5Mbps.

Both forward and reverse rates are doubled in dual-link configuration, in which a serializer and paired deserializer are

connected using two links. Dual-link mode is not available in all GMSL2 device configurations.

Cabling Options

GMSL2 supports operation with either 50Ω Coaxial or 100Ω Shielded-Twisted Pair (STP) cabling.

Coax or STP operation is determined by the state of CXTP at power-up. Set CXTP high for Coax cable drive (single-

ended with default 6Gbps link rate). Set CXTP low for STP mode (differential with default 3Gbps link rate). See the Latch-

On-Power-Up Pins section.

In Coax mode, use only the noninverted SIO pin. AC-couple and terminate the inverting SIO pin using the series

connection of a 100nF capacitor and a 49.9Ω resistor. In STP configurations, both the noninverted and inverted SIO pins

are enabled by default.

Cable attenuation and return loss characteristics must stay within the requirements of the GMSL2 channel specification

to achieve robust full-duplex link performance. These requirements vary with selected link rate. The available link rates

and GMSL2 adaptive equalization enable support of a wide range of cabling options.

Maximum cable length is limited by the frequency-dependent attenuation of the cable. Additionally, PCB and in-line

connectors degrade the return loss characteristic of the cable assembly. The GMSL2 channel specification allows

two inline connectors and provides detailed requirements for cable attenuation and return loss, as well as insertion

loss and return loss requirements for PCB traces. In general, any physical channel implementation compliant with the

GMSL2 channel specification can be used with reliable results. Contact the factory for the GMSL2 channel specification

document.

A 100nF AC-coupling capacitor is normally used for GMSL2 links.

See Figure 15 and Figure 16 for typical GMSL2 serial link configurations.

Line Fault

GMSL2 serializers include a novel line-fault detection circuit. It detects and reports open-circuit, short-to-battery, short-

to-ground, and line-to-line short. The line-fault monitor requires external resistors REXT and RPD connected to the LMN

pins as shown in Figure 15 and Figure 16.

The line-fault monitor is enabled by default, and configuration options are available through registers. Its status can be

read by register. If unmasked, a line fault condition asserts ERRB. Line fault detection cannot be used in conjunction with

power over coax (POC).

The line-fault monitor pins offer flexible connection and programming. On parts with multiple GMSL2 links, either pair (i.e.,

LMN1A/LMN0A) can be used with either link (i.e., SIOA+/SIOA-). In addition, the pins within each pair can be assigned

to either polarity of the link.

MAX96752

GMSL2 Deserializer with Dual LVDS (OLDI)

Output

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