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MAX96752 Datasheet(PDF) 13 Page - Analog Devices |
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MAX96752 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 159 page  Electrical Characteristics (continued) (VDD18 = 1.7V to 1.9V, VDDD = VDDA = 0.95V to 1.05V or VREG = VREGA = 1.7V to 1.9V, VDDIO = 1.7V to 3.6V, TA = -40°C to +105°C, EP connected to PCB ground, typical values are at VDD18 = VDDIO = 1.8V, VDDD = VDDA = 1.0V, TA = 25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AC ELECTRICAL CHARACTERISTICS / I2C TIMING (Note 2) SCL Clock Frequency fSCL Low fSCL range: (I2C MST_BT = 010, I2C SLV_SH = 10) 9.6 100 kHz Mid fSCL range: (I2C MST_BT = 101, I2C SLV_SH = 01) 100 400 High fSCL range: (I2C MST_BT = 111, I2C SLV_SH = 00) 400 1000 Start Condition Hold Time tHD:STA fSCL range, low 4 µs fSCL range, mid 0.6 fSCL range, high 0.26 Low Period of SCL Clock tLOW fSCL range, low 4.7 µs fSCL range, mid 1.3 fSCL range, high 0.5 High Period of SCL Clock tHIGH fSCL range, low 4 µs fSCL range, mid 0.6 fSCL range, high 0.26 Repeated Start Condition Setup Time tSU:STA fSCL range, low 4.7 µs fSCL range, mid 0.6 fSCL range, high 0.26 Data Hold Time tHD:DAT fSCL range, low 0 ns fSCL range, mid 0 fSCL range, high 0 Data Setup Time tSU:DAT fSCL range, low 250 ns fSCL range, mid 100 fSCL range, high 50 Setup Time for Stop Condition tSU:STO fSCL range, low 4 μs fSCL range, mid 0.6 fSCL range, high 0.26 Bus Free Time tBUF fSCL range, low 4.7 μs fSCL range, mid 1.3 fSCL range, high 0.5 Data Valid Time tVD:DAT fSCL range, low 3.45 μs fSCL range, mid 0.9 fSCL range, high 0.45 Data Valid Acknowledge Time tVD:ACK fSCL range, low 3.45 μs fSCL range, mid 0.9 fSCL range, high 0.45 MAX96752 GMSL2 Deserializer with Dual LVDS (OLDI) Output www.analog.com Analog Devices | 13 |
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