AD5674 datasheet(25/31 Pages) AD

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Data Sheet

AD5673R/AD5677R

Rev. 0 | Page 25 of 31

WRITE AND UPDATE COMMANDS

Write to Input Register x (Dependent on LDAC)

Command 0001 allows the user to write the dedicated input

the LDAC mask register.

Update DAC Register x with Contents of Input Register x

Command 0010 loads the DAC registers with the contents of

the input registers selected and updates the DAC outputs

directly. Data Bit D15 to Bit D0 determine which DACs have

data from the input register transferred to the DAC register.

Setting a bit to 1 transfers data from the input register to the

appropriate DAC register.

Write to and Update DAC Channel x (Independent

of LDAC)

Command 0011 allows the user to write to the DAC registers

and updates the DAC outputs directly. The DAC address bits

select the DAC channel.

I2C SLAVE ADDRESS

The AD5673R/AD5677R have a 7-bit I2C slave address. The five

MSBs are 00011, and the two LSBs (A1 and A0) are set by the

state of the A1 and A0 address pins. The ability to make hardwired

changes to A1 and A0 allows the user to incorporate up to four

AD5673R or AD5677R devices on one bus (see Table 11).

Table 11. Device Address Selection

A1 Pin Connection

A0 Pin Connection

GND

VLOGIC

GND

VLOGIC

SERIAL OPERATION

The 2-wire I2C serial bus protocol operates as follows:

1. The master initiates a data transfer by establishing a start

condition when a high to low transition on the SDA line

occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit slave address.

2. The slave device with the transmitted address responds by

pulling SDA low during the ninth clock pulse (this is called

the acknowledge bit, or ACK). At this stage, all other

devices on the bus remain idle while the selected device waits

for data to be written to or read from its input shift register.

4. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit).

Transitions on the SDA line must occur during the low period

of SCL. SDA must remain stable during the high period of SCL.

5. After all data bits are read or written, a stop condition is

established. In write mode, the master pulls the SDA line high

during the 10th clock pulse to establish a stop condition. In

read mode, the master issues a no acknowledge (NACK)

for the ninth clock pulse (that is, the SDA line remains

high). The master then brings the SDA line low before the

10th clock pulse, and then high again during the 10th clock

pulse to establish a stop condition.

WRITE OPERATION

When writing to the AD5673R/AD5677R, begin with a start

command followed by an address byte (R/W = 0), after which

the DAC acknowledges that it is prepared to receive data by pulling

SDA low. The AD5673R/AD5677R require two bytes of data for the

DAC and a command byte to control various DAC functions.

Three bytes of data must therefore be written to the DAC with

the command byte followed by the most significant data byte and

the least significant data byte, as shown in Figure 59. All these data

bytes are acknowledged by the AD5673R/AD5677R. A stop

condition follows.

READ OPERATION

When reading data back from the AD5673R/AD5677R, begin

with a start command followed by an address byte (R/W = 0),

after which the DAC acknowledges that it is prepared to receive

data by pulling SDA low. The address byte must be followed by

the command byte, which determines both the read command

(0x9) that is to follow and the pointer address to read from. The

command byte is also acknowledged by the DAC. The user

configures the channel to read back the contents of one or more

DAC input registers and, using the command byte, sets the

readback command to active. The command byte must be

followed by two dummy bytes of data.

Then, the master establishes a repeated start condition, and the

address is resent with R/W = 1. This byte is acknowledged by the

DAC, indicating that it is prepared to transmit data. Two bytes

of data are then read from the DAC, as shown in Figure 60. A no

acknowledge condition from the master, followed by a stop

condition, completes the read sequence. If more than one DAC

is selected, DAC 0 is read back by default.

MULTIPLE DAC READBACK SEQUENCE

When reading data back from multiple AD5673R/AD5677R

DACs, the user begins with an address byte (R/W = 0), after

which the DAC acknowledges that it is prepared to receive data

by pulling SDA low. The address byte must be followed by the

command byte. The command byte, which determines both the

read command (0x9) that is to follow and the pointer address to

read from, is also acknowledged by the DAC. The user selects

the first channel to read back using the command byte. The

command byte must be followed by two dummy bytes of data.

Following this sequence, the master establishes a repeated start

condition, and the address is resent with R/W = 1. This byte is

acknowledged by the DAC, indicating that it is prepared to

transmit data. The first two bytes of data are then read from

DAC Input Register x (selected using the command byte), MSB

first, as shown in Figure 60.

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