4) For fclk < 5.0 MHz, the clock duty cycle is typically 25 %. But at fclk = 5.0 MHz or

higher a typical of 50% is recommended. This is to keep the die-to-die FPN, fixed

pattern noise, to a minimum between die transitions in CIS operation.

5) Dty is the ratio of clock pulse width over the clock period.

6) Tint at the minimum integration time is specified with a maximum clock frequency of 6.5

MHz. This specification is for a single sensor. When multiple sensors are cascaded in

series, this minimum integration time increases with each additional number of sensors.

Switching Characteristics @ 25

Since these image sensors are applied in multiple-length line array with a wide range in

scanning speeds, two types of output video amplifiers are used. Three video output circuits

are discussed under the section entitled, Output Circuits for Converting the Video Signal. But

there are only two basic types. One is current sensing amplifier and the other is charge

storing buffer amplifier. Simplified block diagrams show their interface connections with the

image sensors. They were also used to measure the specifications given in this data sheet.

The timing relationships among these two different video signals and the image sensor’s two

input clocks, its start pulse, SP, its shift register clock, CP, and its shift register output, EOS,

are shown in two diagrams, Figure 3A and its supplement, Figure 3B. The two timing

diagrams are accompanied with two tables of timing symbol’s specification. These symbols

graphically define the timing relationships among the waveforms in the timing diagrams, see

Figure 3A, Timing Diagram of the PI3039 Sensor. The switching specifications are given in

Table 6A, Timing Symbol’s Definition. Except for the analog video output, the rest are digital

clock waveforms. Their levels are +5 Volts CMOS compatible. The video signal, Iout, timing

is specified in Table 6A. Its amplitude was specified in Table 2, Electro-Optical

Characteristics.

Figure 3A. Timing Diagram of the PI3039 Sensor

(Uses Video Output Circuit in Figure 4B)

PAGE 5 OF 10, PI3039, 12/2/02

to

tprh

CP (CLOCK)

SP (START)

tonoff

tds

tdh

tw

terdl

tdtt

tdtp

FIRST

PIXEL

LAST

PIXEL

tefdl

IOUT

(VIDEO

CURRENT PULSE)

EOS

(END OF

SCAN)