Clock cycle time

154

10000

ns

Clock pulse width

77

ns

Clock duty cycle

25

50

75

%

Data setup time

tds

20

ns

Data hold time

tdh

20

ns

Prohibit crossing time

20

ns

SP turn on and off

Tonoff

(5)

Note 5

EOS rise delay

terdl

80

ns

EOS fall delay

tefdl

75

ns

Signal delay time to

peak

20

ns

Signal fall time delay

80

ns

Table 6A. Timing Symbol's Definition

Notes:

1. Minimum to is specified at the maximum clock frequency of 6.5MHz.

2. Since the clock pulse width varies with frequency, tw will vary according to duty cycle. This

minimum is specified @ 6.5MHz and 50% duty cycle.

3. The clock duty cycle typically is 25 %. At 5.0 MHz or higher 50% is recommended. This

recommendation is to keep the die-to-die FPN, fixed pattern noise, to a minimum between

die transitions in CIS operation.

4. Tprh is the time where the start pulse high is prohibited. No consecutive falling clock edges

are allowed during one cycle of SP. Otherwise, two start pulses or more will load into the

shift register for each negative going clock edge. Multiple start pulses loaded into the shift

register will access proportional numbers of multiple pixels simultaneously at each clock

cycle.

5. The recommended time to start and stop the SP is between two consecutive rising clock

edges, indicated by the tonoff arrows.

6. These values, tdtp and tftd, are measurements from the circuit in Figure 4B, which is

essentially the pulse voltage across the 50 ohm resistor. This is one of circuit employed to

convert the Video Signal current to voltage. See discussion on the two amplifier

configurations under the section entitled, Output Circuits for Converting the Video Signal.

Figure 3B. Supplement Timing Diagram

This supplementary timing diagram, Figure 3B, Supplement Timing Diagram, graphically

defines the symbols used to describe timing relationship between the waveforms at the output

Item

Symbol

Minimum

Mean

Maximum

Units

PAGE 6 OF 10, PI3039, 12/2/02

CP

VIDEO

OUTPUT

Vp

to

tsmp

Dark Level

Vd

Reset Level

tvf