it opens just prior to the next following pixel readout. This reset is active during CP’s high

state. The disadvantage of this circuit is that it has negative going output and will have pulse

shape of the current impulse that decays over a long period. Hence, it may not be desirable

at low clock sample frequencies.

To get around this decaying type of sampling pixels, this second circuit may be more

desirable. See Figure 4B, Voltage Buffer Amplifier. This method uses the video line as

storage medium. It uses a buffer amplifier and buffers the video line with its high input

impedance. Hence, the video line effectively approaches the condition of an open circuit and

becomes a capacitance that is proportional to video line length and geometry. When the

photo site produces the signal current, it charges the video line capacitance and converts the

output into a voltage signal. The switch, SW, is a video line reset switch. It resets the video

line and the photo-site presently under interrogation, just prior to the next following pixel

readout. This reset is active during CP’s high state.

Figure 4B, Voltage Buffer Amplifier, shows the buffer amplifier configuration. The general

video wave shape and timing characteristics of this circuit are discussed under section entitled

Switching Characteristics @ 25

general signal wave shape and its timing relationship to the clock. Its accompanying Table 6B,

Supplement Timing Symbol's Definition, defines the symbols used in the Figure 3B. This

circuit is generally employed in CIS applications where the clock speeds are under 5.0MHz.

Figure 4B. Voltage Buffer Amplifier

This video line charging implementation is extensively used because its simplicity and low

cost. However, speed is limited because of the video line capacitance. For any given video

line capacitance, the rate of signal charge remains the same, hence, the charging slope. As

the sampling frequency is increased, the pixel’s signal window decreases, reducing the

amplitude and at very high frequency the video sample become triangular in shape. This

effect is especially prevalent when longer line arrays are implemented. However, the CIS

modules are cascaded structure of N Image sensors in series to form various lengths of line

arrays. It is easy to see that as N increases the length of the video line on the PCB increases,

thus, increasing the video line capacitance and making it difficult to extract the signal,

especially, at high speeds.

IOUT

PAGE 9 OF 10, PI3039, 12/2/02

Video

Output

SW

RIN

RFB

OP-AMP

From all

sensor video