Preliminary PI3041A datasheet

Switching Characteristics @ 25

The timing relationships of the video output voltage and its two input clocks the start pulse, SP, and

the shift register clock, CP, along with the shift register EOS output clock are shown in Figure 7,

Timing Diagram Of The PI3041A Sensor.

timing diagram is given in Table 9, Timing Symbol's Definition below the timing diagram. The digital

clocks' levels are +5 Volts CMOS compatible. The video, IOUT, is defined in Figure 4, Video Pixel

Output in section Output Circuit Of The Image Sensor.

Figure 7. Timing Diagram Of The PI3041A Sensor

Item

Symbol

Minimum

Mean

Maximum

Units

Clock cycle time

to

200

10000

ns

Clock pulse width

(1)

tw

50

ns

Clock duty cycle

25

50

75

%

Data setup time

tds

20

ns

Data hold time

tdh

20

ns

Prohibit crossing time

(2)

tprh

20

ns

EOS rise delay

terdl

60

ns

EOS fall delay

tefdl

70

ns

Signal delay time

(3)

tdl

20

ns

Signal settling time

(3)

ts/h

120

ns

Table 9. Timing Symbol's Definition

Notes (1)

The clock pulse width, tw, varies with frequency, as well as, the duty cycle.

Page 15 of 18 Date: 09/23/05