NXP Semiconductors

CD1020

22-channel multiple switch detection interface

8.10 SPI control register definition

A 32-bit SPI allows the system microprocessor to configure the CD1020 for each input as well as read out the status of each input. The SPI also allows the Fault

Status and INTflg bits to be read via the SPI. The SPI MOSI bit definitions are given in Table 8:

Register #

Register name

Address

R/W

0

SPI check

0

0

0

0

0

0

0

0

02/03

Device configuration register

0

0

0

0

0

0

1

0/1

04/05

Tri-state SP register

0

0

0

0

0

1

0

0/1

06/07

Tri-state SG register

0

0

0

0

0

1

1

0/1

08/09

Wetting current level SP register

0

0

0

0

1

0

0

0/1

0A/0B

Wetting current level SG register 0

0

0

0

0

1

0

1

0/1

0C/0D

Wetting current level SG register 1

0

0

0

0

1

1

0

0/1

16/17

Continuous wetting current SP register

0

0

0

1

0

1

1

0/1

18/19

Continuous Wetting Current SG Register

0

0

0

1

1

0

0

0/1

1A/1B

Interrupt enable SP register

0

0

0

1

1

0

1

0/1

1C/1D

Interrupt enable SG register

0

0

0

1

1

1

0

0/1

1E/1F

Low-power mode configuration

0

0

0

1

1

1

1

0/1

20/21

Wake-up enable register SP

0

0

1

0

0

0

0

0/1

22/23

Wake-up enable register SG

0

0

1

0

0

0

1

0/1

24/25

Comparator only SP

0

0

1

0

0

1

0

0/1

26/27

Comparator only SG

0

0

1

0

0

1

1

0/1

28/29

LPM voltage threshold SP configuration

0

0

1

0

1

0

0

0/1

2A/2B

LPM voltage threshold SG configuration

0

0

1

0

1

0

1

0/1

2C/2D

Polling current SP configuration

0

0

1

0

1

1

0

0/1

2E/2F

Polling current SG configuration

0

0

1

0

1

1

1

0/1

39

Enter low-power mode

0

0

1

1

1

0

0

1

3A/3B

AMUX control register

0

0

1

1

1

0

1

0/1

Table 3. MOSI input register bit definition

CD1020

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Product data sheet

Rev. 5 — 20 August 2024

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