CD1020 datasheet(13/61 Pages) NXP

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NXP Semiconductors

CD1020

22-channel multiple switch detection interface

• Input switch change of state (when enabled)

• Falling edge of WAKE_B (as set by the device configuration register)

• Falling edge of INT_B (with VDDQ = 5.0 V)

• Falling edge of CS_B (with VDDQ = 5.0 V)

• Power-On-Reset (POR)

The VDDQ supply may be removed from the device during LPM, however removing VDDQ from the device

disables a wake-up from falling edge of INT_B and CS_B. The IC checks the status of VDDQ after a falling edge

of WAKE_B (as selected in the device configuration register), INT_B and CS_B. The IC returns to LPM and

does not report a Wake event, if VDDQ is low. If the VDDQ is high, the IC wakes up and reports the Wake event.

In cases where CS_B is used to wake the device, the first MISO data message is not valid.

The LPM command contains setting of the polling timer, as shown in Table 23. The polling timer is used

periodically to poll the inputs during low-power mode to check for change of states. The tACTIVEPOLL time is

the length of time the part is active during the polling timer to check for change of state. The low-power mode

voltage threshold allows the user to determine the noise immunity versus lower current levels that polling

allows. Figure 13 shows the polling operation.

When an input is determined to meet the condition Open (when entering LPM), yet while Open (on polling

event) the chip does not continue the polling event for that input(s) to lower current in the chip (Figure 12 shows

SG, SB is logically the same).

aaa-056368

55 μs

Polling timer

(64 ms def)

Voltage on SG pin

Latch voltage

LPM voltage threshold

(~0.25 V)

Compare voltage to initial

(Delta > 0.25 or > 4.0 V)

End polling (current off if

no change detected)

Figure 6. Low-power mode polling check

CD1020

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Product data sheet

Rev. 5 — 20 August 2024

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