CD1020 datasheet(12/61 Pages) NXP

12 / 61 page

NXP Semiconductors

CD1020

22-channel multiple switch detection interface

above the UV threshold (~4.3 V rising). The internal fuses read in approximately 50 μs and the chip enters the

normal mode.

8.1.3 Normal mode

In normal mode, the chip operates as selected in the available registers. Any command may be loaded in

normal mode, although not all (low-power mode) registers are used in the normal mode. All the LPM registers

must be programmed in Normal mode as the SPI is not active in LPM. The normal mode of the chip is used to:

• Operate the AMUX

• Communicate via the SPI

• Interrupt the IC, wetting and sustain currents, and the thresholds available to use

The WAKE_B pin is asserted (low) in normal mode and can be used to enable a power supply (ENABLE_B).

Various fault detections are available in this mode including overvoltage, overtemperature, thermal warning, SPI

errors, and Hash faults.

8.1.4 Low-power mode

When the user needs to lower the IC current consumption, a low-power mode is used. The only method to enter

LPM is through a SPI word. After the chip is in low-power mode, the majority of circuitry is turned off including

most power rails, the 4.0 MHz oscillator, and all the fault detection circuits. This mode is the lowest current

consumption mode on the chip. If a fault occurs while the chip is in this mode, the chip does not see or register

the fault (does not report via the SPI when awakened). Some items may wake the IC in this mode, including

the interrupt timer, falling edge of INT_B, CS_B, or WAKE_B (configurable), or a comparator-only mode switch

detection.

8.1.5 Polling mode

The CD1020 uses a polling mode that periodically (selectable in LPM config register) interrogates the input

pins to determine in what state the pins are, and decides if there was a change of state from when the chip

was in normal mode. There are various configurations for this mode, which allow the user greater flexibility in

operation. This mode uses the current sources to pull up (SG) or pull down (SB) to determine if a switch is open

or closed. More information is available in section 7.2, "Low-power mode operation".

In the case of a low VBATP, the polling pauses and waits until the VBATP rises out of UV or a POR occurs. The

pause of the polling ensures all of the internal rails, currents, and thresholds are up at the required levels to

accurately detect open or closed switches. The chip does not wake-up in this condition and simply waits for the

VBATP voltage to rise or cause a POR.

After the polling ends, the chip either returns to the low-power mode, or enters normal mode when a wake event

is detected. Other events may wake the chip as well, such as the falling edge of CS_B, INT_B, or WAKE_B

(configurable). A comparator only mode switch detection is always on in LPM or Polling mode, therefore, a

change of state for those inputs would effectively wake the IC in Polling mode as well.

If the Wake-up enable bits are disabled on all channels (SG and SP), the device will not wake up with a change

of state on any of the input pins. In this case, the device will disable the polling timer to allow the lowest current

consumption during low-power mode.

8.2 Low-power mode operation

Low-power mode (LPM) is used to reduce system quiescent currents. LPM may be entered only by sending the

Enter Low-power mode command. All register settings programmed in normal mode are maintained while in

LPM.

The CD1020 exits LPM and enter normal mode when any of the following events occur:

CD1020

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 20 August 2024

Document feedback

12 / 61

CD1020 Datasheet(PDF) 12 Page - NXP Semiconductors

CD1020 Datasheet(HTML) 12 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL