LTM4613 datasheet(15/30 Pages) LINER

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LTM4613

4613fd

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APPLICATIONS INFORMATION

Ratiometric tracking can be achieved by a few simple cal-

culations and the slew rate value applied to the master’s

TRACK/SS pin. The TRACK/SS pin has a control range

from 0 to 0.6V. The master’s TRACK/SS pin slew rate is

directly equal to the master’s output slew rate in Volts/

Time. The equation:

•100k =R2

where MR is the master’s output slew rate and SR is the

slave’s output slew rate in Volts/Time. When coincident

tracking is desired, then MR and SR are equal, thus R2 is

equal to 100k. R1 is derived from equation:

R1=

0.6V

VFB

100k

VFB

RFB

–

VTRACK

where VFB is the feedback voltage reference of the regula-

tor, and VTRACK is 0.6V. Since R2 is equal to the 100k top

feedback resistor of the slave regulator in equal slew rate

or coincident tracking, then R1 is equal to RFB with VFB =

VTRACK. Therefore R2 = 100k, and R1 = 5.23k in Figure 5.

In ratiometric tracking, a different slew rate maybe desired

for the slave regulator. R2 can be solved for when SR is

slower than MR. Make sure that the slave supply slew

rate is chosen to be fast enough so that the slave output

voltage will reach its final value before the master output.

For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then

R2 = 125k. Solve for R1 to equal 5.18k.

Each of the TRACK/SS pins will have the 1.5µA current

source on when a resistive divider is used to implement

trackingonthatspecificchannel. Thiswillimposeanoffset

on the TRACK/SS pin input. Smaller values resistors with

the same ratios as the resistor values calculated from

the above equation can be used. For example, where the

100k is used then a 10k value can be used to reduce the

TRACK/SS pin offset to a negligible value.

RUN Enable

The RUN pin is used to enable the power module. The

pin has an internal 5.1V Zener to ground. The pin can be

driven with 5V logic levels.

The RUN pin can also be used as an undervoltage lockout

(UVLO) function by connecting a resistor divider from

the input supply to the RUN pin. The equation for UVLO

threshold:

VUVLO =

RA +RB

•1.5V

where RA is the top resistor, and RB is the bottom resistor.

Refer to Figure 1, Simplified Block Diagram.

Power Good

The PGOOD pin is an open-drain pin that can be used to

monitor valid output voltage regulation. This pin monitors

a ±10% window around the regulation point and tracks

with margining.

COMP Pin

This pin is the external compensation pin. The module

has already been internally compensated for most output

voltages. LTpowerCAD is available for other control loop

optimization.

FCB Pin

The FCB pin determines whether the bottom MOSFET

remains on when current reverses in the inductor. Tying

this pin above its 0.6V threshold enables discontinuous

operation where the bottom MOSFET turns off when in-

ductor current reverses. FCB pin below the 0.6V threshold

forcescontinuoussynchronousoperation,allowingcurrent

to reverse at light loads and maintaining high frequency

operation.

PLLIN Pin

The power module has a phase-locked loop comprised

of an internal voltage controlled oscillator and a phase

detector. This allows the internal top MOSFET turn-on

to be locked to the rising edge of an external clock. The

external clock frequency range must be within ±30%

around the set operating frequency. A pulse detection

circuit is used to detect a clock on the PLLIN pin to turn

on the phase-locked loop. The pulse width of the clock

has to be at least 400ns. The clock high level must be

above 2V and clock low level below 0.3V. The PLLIN pin

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