P89V660 datasheet(39/89 Pages) NXP

39 / 89 page

P89V660_662_664_1

Product data sheet

Rev. 01 — 2 May 2007

39 of 89

NXP Semiconductors

P89V660/662/664

80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin, T0 or T1. In this function, the external input is sampled

once every machine cycle.

When the samples show a high in one cycle and a low in the next cycle, the count is

incremented. The new count value appears in the register in the machine cycle following

the one in which the transition was detected. Since it takes two machine cycles (12

oscillator periods) for 1-to-0 transition to be recognized, the maximum count rate is 1

⁄

12 of

the oscillator frequency. There are no restrictions on the duty cycle of the external input

signal, but to ensure that a given level is sampled at least once before it changes, it should

be held for at least one full machine cycle. In addition to the ‘Timer’ or ‘Counter’ selection,

Timer 0 and Timer 1 have four operating modes from which to select.

The ‘Timer’ or ‘Counter’ function is selected by control bits C/T in the Special Function

selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both

Timers/Counters. Mode 3 is different. The four operating modes are described in the

following text.

Table 26.

TMOD - Timer/Counter mode control register (address 89H) bit allocation

Not bit addressable; Reset value: 0000 0000B; Reset source(s): any source

Bit

Symbol

T1GATE

T1C/T

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

Table 27.

TMOD - Timer/Counter mode control register (address 89H) bit description

Bit

Symbol

Description

T1GATE

Gating control for Timer 1. When set, Timer/Counter is enabled only

while the INT1 pin is high and the TR1 control pin is set. When

cleared, Timer 1 is enabled when the TR1 control bit is set.

T1C/T

Timer or Counter select for Timer 1. Cleared for Timer operation (input

from CCLK). Set for Counter operation (input from T1 input pin).

T1M1

Mode select for Timer 1.

T1M0

T0GATE

Gating control for Timer 0. When set, Timer/Counter is enabled only

while the INT0 pin is high and the TR0 control pin is set. When

cleared, Timer 0 is enabled when the TR0 control bit is set.

T0C/T

Timer or Counter select for Timer 0. Cleared for Timer operation (input

from CCLK). Set for Counter operation (input from T0 input pin).

T0M1

Mode Select for Timer 0.

T0M0

Table 28.

TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating

mode

Operating mode

8048 timer ‘TLx’ serves as 5-bit prescaler.

16-bit Timer/Counter ‘THx’ and ‘TLx' are cascaded;

there is no prescaler.

P89V660 Datasheet(PDF) 39 Page - NXP Semiconductors

P89V660 Datasheet(HTML) 39 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

Datasheet Download

Link URL