P89V660 datasheet(49/89 Pages) NXP

49 / 89 page

P89V660_662_664_1

Product data sheet

Rev. 01 — 2 May 2007

49 of 89

NXP Semiconductors

P89V660/662/664

80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI

6.7.1 Mode 0

Serial data enters and exits through RXD and TXD outputs the shift clock. Only 8 bits are

transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at 1

⁄

6 of the CPU clock frequency.

UART conﬁgured to operate in this mode outputs serial clock on TXD line no matter

whether it sends or receives data on RXD line.

6.7.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8

data bits (LSB ﬁrst), and a stop bit (logical 1). When data is received, the stop bit is stored

in RB8 in Special Function Register SCON. The baud rate is variable and is determined

by the Timer 1

⁄

2 overﬂow rate.

6.7.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logical 0), 8

data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logical 1). When data is

transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or (e.g. the

parity bit (P, in the PSW) could be moved into TB8). When data is received, the 9th data

bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The

baud rate is programmable to either 1

⁄

16 or

⁄

32 of the CPU clock frequency, as determined

by the SMOD1 bit in PCON.

6.7.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8

data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logical 1). In fact, Mode 3

is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is

variable and is determined by the Timer 1

⁄

2 overﬂow rate.

Table 37.

SCON - Serial port control register (address 98H) bit allocation

Bit addressable; Reset value: 00H

Bit

Symbol

SM0/FE

SM1

SM2

REN

TB8

RB8

Table 38.

SCON - Serial port control register (address 98H) bit description

Bit

Symbol

Description

SM0/FE

The usage of this bit is determined by SMOD0 in the PCON register. If

SMOD0 = 0, this bit is SM0, which with SM1, deﬁnes the serial port

mode. If SMOD0 = 1, this bit is FE (Framing Error). FE is set by the

receiver when an invalid stop bit is detected. Once set, this bit cannot

be cleared by valid frames but can only be cleared by software. (Note:

It is recommended to set up UART mode bits SM0 and SM1 before

setting SMOD0 to ‘1’.)

SM1

With SM0, deﬁnes the serial port mode (see Table 39 below).

SM2

Enables the multiprocessor communication feature in Modes 2 and 3.

In Mode 2 or 3, if SM2 is set to ‘1’, then Rl will not be activated if the

received 9th data bit (RB8) is ‘0’. In Mode 1, if SM2 = 1 then RI will not

be activated if a valid stop bit was not received. In Mode 0, SM2

should be ‘0’.

REN

Enables serial reception. Set by software to enable reception. Clear by

software to disable reception.

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