M68HC08 datasheet(156/288 Pages) FREESCALE

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Analog-to-Digital Converter (ADC)

Data Sheet

MC68HC908BD48 — Rev. 2.1

156

Analog-to-Digital Converter (ADC)

Freescale Semiconductor

or DDR will not have any affect on the port pin that is selected by the

ADC. Read of a port pin which is in use by the ADC will return an

unknown state if the corresponding DDR bit is at logic 0. If the DDR bit

is at logic 1, the value in the port data latch is read.

12.4.2 Voltage Conversion

When the input voltage to the ADC equals

VDD, the ADC converts the

signal to $FF (full scale). If the input voltage equals VSS, the ADC

converts it to $00. Input voltage between

VDD and VSS are a

straight-line linear conversion. All other input voltages will result in $FF

if greater than

VDD and $00 if less than VSS.

NOTE:

Input voltage should not exceed the analog supply voltages.

12.4.3 Conversion Time

Twelve ADC internal clocks are required to perform one conversion. The

ADC starts a conversion on the first rising edge of the ADC internal clock

immediately following a write to the ADSCR. If the ADC internal clock is

selected to run at 1MHz, then one conversion will take 12

µs to complete.

With a 1MHz ADC internal clock the maximum sample rate is 83.3kHz.

12.4.4 Continuous Conversion

In the continuous conversion mode, the ADC continuously converts the

selected channel filling the ADC data register with new data after each

conversion. Data from the previous conversion will be overwritten

whether that data has been read or not. Conversions will continue until

the ADCO bit is cleared. The COCO bit (ADC status control register,

$005D) is set after each conversion and can be cleared by writing the

ADC status and control register or reading of the ADC data register.

-------

12 ADC Clock Cycles

Conversion Time =

ADC Clock Frequency

Number of Bus Cycles = Conversion Time

× Bus Frequency

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