M68HC08 datasheet(157/288 Pages) FREESCALE

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Analog-to-Digital Converter (ADC)

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

Analog-to-Digital Converter (ADC)

157

12.4.5 Accuracy and Precision

The conversion process is monotonic and has no missing codes.

12.5 Interrupts

When the AIEN bit is set, the ADC module is capable of generating a

CPU interrupt after each ADC conversion. A CPU interrupt is generated

if the COCO bit is at logic 0. The COCO bit is not used as a conversion

complete flag when interrupts are enabled.

12.6 Low-Power Modes

The following subsections describe the low-power modes.

12.6.1 Wait Mode

The ADC continues normal operation during wait mode. Any enabled

CPU interrupt request from the ADC can bring the MCU out of wait

mode. If the ADC is not required to bring the MCU out of wait mode,

power down the ADC by setting the ADCH[4:0] bits in the ADC status

and control register to logic 1’s before executing the WAIT instruction.

12.6.2 Stop Mode

The ADC module is inactive after the execution of a STOP instruction.

Any pending conversion is aborted. ADC conversions resume when the

MCU exits stop mode. Allow one conversion cycle to stabilize the analog

circuitry before attempting a new ADC conversion after exiting stop

mode.

12.7 I/O Signals

The ADC module has 6 channels that are shared with I/O port C.

M68HC08 Datasheet(PDF) 157 Page - Freescale Semiconductor, Inc