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M68HC08 Datasheet(PDF) 161 Page - Freescale Semiconductor, Inc |
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M68HC08 Datasheet(HTML) 161 Page - Freescale Semiconductor, Inc |
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161 / 288 page  Analog-to-Digital Converter (ADC) MC68HC908BD48 — Rev. 2.1 Data Sheet Freescale Semiconductor Analog-to-Digital Converter (ADC) 161 12.8.3 ADC Input Clock Register This register selects the clock frequency for the ADC. ADIV2:ADIV0 — ADC Clock Prescaler Bits ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 12-3 shows the available clock configurations. The ADC clock should be set to approximately 1MHz. With an internal bus frequency of 6MHz, set ADIV[2:0] = 010, for a divide by four ADC clock rate. Address: $005F Bit 7 654321 Bit 0 Read: ADIV2 ADIV1 ADIV0 00000 Write: Reset: 00000000 = Unimplemented Figure 12-4. ADC Input Clock Register (ADICLK) Table 12-3. ADC Clock Divide Ratio ADIV2 ADIV1 ADIV0 ADC Clock Rate 0 0 0 Internal bus clock ÷ 1 0 0 1 Internal bus clock ÷ 2 0 1 0 Internal bus clock ÷ 4 0 1 1 Internal bus clock ÷ 8 1 X X Internal bus clock ÷ 16 X = don’t care |
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