DS2155 datasheet(6/238 Pages) DALLAS

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DS2155

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1.1 Table of Figures

Figure 3-1. Block Diagram........................................................................................................................................ 15

Figure 3-2. Receive and Transmit LIU...................................................................................................................... 16

Figure 3-3. Receive and Transmit Framer/HDLC ..................................................................................................... 17

Figure 3-4. Backplane Interface ................................................................................................................................ 18

Figure 4-1. 10mm CSBGA Pin Configuration .......................................................................................................... 32

Figure 6-1. Programming Sequence .......................................................................................................................... 39

Figure 8-1. Clock Map............................................................................................................................................... 45

Figure 16-1. Simplified Diagram of Receive Signaling Path .................................................................................... 83

Figure 16-2. Simplified Diagram of Transmit Signaling Path................................................................................... 89

Figure 20-1. CRC-4 Recalculate Method ................................................................................................................ 109

Figure 24-1. Typical Monitor Application .............................................................................................................. 144

Figure 24-2. CMI Coding ........................................................................................................................................ 146

Figure 24-3. Software-Selected Termination, Metallic Protection.......................................................................... 156

Figure 24-4. Software-Selected Termination, Longitudinal Protection................................................................... 157

Figure 24-5. E1 Transmit Pulse Template............................................................................................................... 159

Figure 24-6. T1 Transmit Pulse Template............................................................................................................... 159

Figure 24-7. Jitter Tolerance.................................................................................................................................... 160

Figure 24-8. Jitter Tolerance (E1 Mode) ................................................................................................................. 160

Figure 24-9. Jitter Attenuation (T1 Mode) .............................................................................................................. 161

Figure 24-10. Jitter Attenuation (E1 Mode) ............................................................................................................ 161

Figure 24-11. Optional Crystal Connections ........................................................................................................... 162

Figure 26-1. Simplified Diagram of BERT in Network Direction .......................................................................... 171

Figure 26-2. Simplified Diagram of BERT in Backplane Direction ....................................................................... 171

Figure 28-1. IBO Example ...................................................................................................................................... 186

Figure 29-1. ESIB Group of Four DS2155s ............................................................................................................ 187

Figure 33-1. T1 Transmit Flow Diagram ................................................................................................................ 194

Figure 33-2. E1 Transmit Flow Diagram ................................................................................................................ 195

Figure 34-1. JTAG Functional Block Diagram ....................................................................................................... 199

Figure 34-2. TAP Controller State Diagram............................................................................................................ 202

Figure 35-1. Receive-Side D4 Timing..................................................................................................................... 208

Figure 35-2. Receive-Side ESF Timing................................................................................................................... 208

Figure 35-3. Receive-Side Boundary Timing (Elastic Store Disabled)................................................................... 209

Figure 35-4. Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).................................................. 209

Figure 35-5. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).................................................. 210

Figure 35-6. Transmit-Side D4 Timing ................................................................................................................... 210

Figure 35-7. Transmit-Side ESF Timing ................................................................................................................. 211

Figure 35-8. Transmit-Side Boundary Timing (with Elastic Store Disabled) ......................................................... 211

Figure 35-9. Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) ................................................ 212

Figure 35-10. Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) .............................................. 212

Figure 35-11. Receive-Side Timing ........................................................................................................................ 213

Figure 35-12. Receive-Side Boundary Timing (with Elastic Store Disabled)......................................................... 213

Figure 35-13. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (Elastic Store Enabled) ........................ 214

Figure 35-14. Receive-Side Boundary Timing, RSYSCLK = 2.048MHz (Elastic Store Enabled) ........................ 214

Figure 35-15. Receive IBO Channel Interleave Mode Timing ............................................................................... 215

Figure 35-16. Receive IBO Frame Interleave Mode Timing................................................................................... 216

Figure 35-17. G.802 Timing, E1 Mode Only .......................................................................................................... 217

Figure 35-18. Transmit-Side Timing....................................................................................................................... 217

Figure 35-19. Transmit-Side Boundary Timing (Elastic Store Disabled) ............................................................... 218

Figure 35-20. Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz (Elastic Store Enabled) ...................... 218

Figure 35-21. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz (Elastic Store Enabled) ....................... 219

Figure 35-22. Transmit IBO Channel Interleave Mode Timing.............................................................................. 220

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