DS2155 datasheet(137/238 Pages) DALLAS

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DS2155

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INFO5, INFO6

HDLC #1 Information Register

HDLC #2 Information Register

2Eh, 2Fh

Bit #

Name

—

TEMPTY

TFULL

REMPTY

PS2

PS1

PS0

Default

Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time bits indicating the status as of the last read of

the receive FIFO.

PS2

PS1

PS0

Packet Status

In Progress

Packet OK: Packet ended with correct CRC codeword

CRC Error: A closing flag was detected, preceded by a corrupt CRC

codeword

Abort: Packet ended because an abort signal was detected (seven or

more 1s in a row).

Overrun: HDLC controller terminated reception of packet because

receive FIFO is full.

Bit 3/Receive FIFO Empty (REMPTY). A real-time bit that is set high when the receive FIFO is empty.

Bit 4/Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.

Bit 5/Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty.

INFO4

HDLC Event Information Register #4

2Dh

Bit #

Name

—

H2UDR

H2OBT

H1UDR

H1OBT

Default

Bit 0/HDLC #1 Opening Byte Event (H1OBT). Set when the next byte available in the receive FIFO is the first

byte of a message.

Bit 1/HDLC #1 Transmit FIFO Underrun Event (H1UDR). Set when the transmit FIFO empties out without

having seen the TMEND bit set. An abort is automatically sent. This bit is latched and is cleared when read.

Bit 2/HDLC #2 Opening Byte Event (H2OBT). Set when the next byte available in the receive FIFO is the first

byte of a message.

Bit 3/HDLC #2 Transmit FIFO Underrun Event (H2UDR). Set when the transmit FIFO empties out without

having seen the TMEND bit set. An abort is automatically sent. This bit is latched and is cleared when read

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