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THERMAL RESISTANCE FOR TSSOP (PW) PACKAGE

(1)

RECOMMENDED OPERATING CONDITIONS

RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS

(1)

EEPROM SPECIFICATION

CDCE949

CDCEL949

SCAS844 – JUNE 2007

AIRFLOW

TSSOP24

PARAMETER

(lfm)

°C/W

0

85

150

80

Thermal Resistance Junction to Ambient

250

78

500

76

Thermal Resistance Junction to Case

—

26

(1)

The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

MIN

NOM

MAX

UNIT

Device supply voltage

1.7

1.8

1.9

V

CDCE949

2.3

3.6

Output Yx supply

V

voltage

CDCEL949

1.7

1.9

Low level input voltage LVCMOS

0.3

× V

DD

V

High level input voltage LVCMOS

0.7

× V

DD

V

Input voltage threshold LVCMOS

0.5

× V

DD

V

Input voltage range S0

0

1.9

V

Input voltage range S1,

0

3.6

S2, SDA, SCL

Input voltage range CLK

0

1.9

V

±12

mA

Output current

±10

mA

±8

mA

Output load LVCMOS

10

pF

Operating free-air temperature

–40

85

°C

MIN

NOM

MAX

UNIT

Crystal Input frequency range (fundamental mode)

8

27

32

MHz

ESR

Effective series resistance

100

Ω

Pulling range (0 V

≤ V

(2)

±120

±150

ppm

Frequency control voltage

0

V

Pullability ratio

220

On-chip load capacitance at Xin and Xout

0

20

pF

(1)

For more information about VCXO configuration and crystal recommendation see application report SCAA085.

(2)

Pulling range depends on crystal type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min

±120 ppm

applies for crystal listed in the application report SCAA085.

MIN

TYP

MAX

UNIT

EEcyc

EEcyc programming cycles of EEPROM

1000

cycles

EEret

EEret data retention

10

years

4

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