CDCE949 datasheet(24/31 Pages) TI

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CDCE949

CDCEL949

SCAS844 – JUNE 2007

Table 13. PLL4 Configuration Register (continued)

OFFSET(1)

Bit(2)

Acronym

Default(3)

DESCRIPTION

48h

7:0

PLL4_0N [11:4

PLL4_0: 30-Bit Multiplier/Divider value for frequency fVCO4_0

004h

(for more information see paragraph PLL Multiplier/Divider Definition)

49h

7:4

PLL4_0N [3:0]

3:0

PLL4_0R [8:5]

000h

4Ah

7:3

PLL4_0R[4:0]

2:0

PLL4_0Q [5:3]

10h

4Bh

7:5

PLL4_0Q [2:0]

4:2

PLL4_0P [2:0]

010b

fVCO4_0 range selection:

00 – fVCO4_0 < 125 MHz

01 – 125 MHz

≤ f

VCO4_0 < 150 MHz

1:0

VCO4_0_RANGE

00b

10 – 150 MHz

≤ f

VCO4_0 < 175 MHz

11 – fVCO4_0 ≥ 175 MHz

4Ch

7:0

PLL4_1N [11:4]

PLL4_1: 30-Bit Multiplier/Divider value for frequency fVCO4_1

004h

(for more information see paragraph PLL Multiplier/Divider Definition)

4Dh

7:4

PLL4_1N [3:0]

3:0

PLL4_1R [8:5]

000h

4Eh

7:3

PLL4_1R[4:0]

2:0

PLL4_1Q [5:3]

10h

4Fh

7:5

PLL4_1Q [2:0]

4:2

PLL4_1P [2:0]

010b

fVCO4_1 range selection:

00 – fVCO4_1 < 125 MHz

01 – 125 MHz

≤ f

VCO4_1 < 150 MHz

1:0

VCO4_1_RANGE

00b

10 – 150 MHz

≤ f

VCO4_1 < 175 MHz

11 – fVCO4_1 ≥ 175 MHz

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