AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
DS030100-U006a
- 4 -
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Min
Typ
Max
Unit
Comment
DC Power Supplies
AVDD(2)
BVDD
DVDD
-0.5
-
5.5 V
V
AVSS, BVSS, DVSS and SVSS all
held to 0.0 V a
xVDD to xVDD Offset
-0.5
0.5
V
Ideally all supplies should be at the
same voltage
Package Power Dissipation
Pmax 25°C
Pmax 85°C
-
-
1.8
0.73
W
Still air, No heatsink, 4 layer board,
44 pins.
θja = 55°C/W
Analog and Digital Input Voltage
Vinmax
Vss-0.5
-
Vdd+0.5
V
Ambient Operating Temperature
Top
-40
-
85
°C
Storage Temperature
Tstg
-65
150
°C
a
Absolute Maximum DC Power Supply Rating - The failure mode is non-catastrophic for Vdd of up to 7 volts, but will cause reduced
operating life time. The additional stress caused by higher local electric fields within the CMOS circuitry may induce metal migration,
oxide leakage and other time/quality related issues.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Comment
DC Power Supplies
AVDD(2)
BVDD
DVDD
4.75
5.00
5.25
V
AVSS, BVSS, DVSS and SVSS all
held to 0 V
Analog Input Voltage.
Vina
VMR-1.9
-
VMR+1.9
V
VMR is 2.0 volts above AVSS
Digital Input Voltage
Vind
0
-
DVDD
V
Junction Temp
Tj
-40
-
125
°C
Assume a package
θja = 55°C/W b
b
In order to calculate the junction temperature you must first empirically determine the current draw (total Idd) for the design. Once the
current consumption established then the following formula can be used; Tj = Ta + Idd x Vdd x 55 °C/W, where Ta is the ambient
temperature. The worst case
θja of 55 °C/W assumes no air flow and no additional heatsink of any type.
General Digital I/O Characteristics (Vdd = 5v +/- 10%, -40 to 85 deg.C)
Parameter
Symbol
Min
Typ
Max
Unit
Comment
Input Voltage Low
Vih
0
-
30
-
% of DVDD
Input Voltage High
Vil
70
-
100
-
% of DVDD
Output Voltage Low
Vol
0
-
20
-
% of DVDD
Output Voltage High
Voh
80
-
100
-
% of DVDD
Input Leakage Current
Iil
-
-
±1.0
µA
All pins except DCLK
Input Leakage Current
Iil
-
±12.0
-
µA
DCLK if a crystal is connected and
the on-chip oscillator is used
Max. Capacitive Load
Cmax
-
-
10
pF
The maximum load for a digital
output is 10 pF // 10 Kohm
Min. Resistive Load
Rmin
10
-
-
Kohm
The maximum load for a digital
output is 10 pF // 10 Kohm
DCLK Frequency
Fmax
-
-
40
MHz
For MODE = 1, Max DCLK is
16 MHz
ACLK Frequency
Fmax
-
-
40
MHz
Divide down to <8 MHz prior to use
as a CAB clock
Clock Duty Cycle
-
45
-
55
%
All clocks
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
