SPEC No.

LC9

LC9

LC9

LC98109A

8109A

8109A

8109A

MODEL No.

LM

LM

LM

LM8M64

8M64

8M64

8M64

PAGE

24

24

24

24

10.

Supply voltage sequence condition

1500 ms MIN. (NOTE 1)

a

e

1s MIN

VDD

YD

LP

XCK

Interface timing active operation

DATA

M

c

f

(NOTE 2)

DISP

b

VDD

3 V

2 V

2 V

1.5V

“VSS”

d

g

Fig.15 Supply voltage sequence condition

(NOTE 1) Power ON/OFF cycle time. All signals and power line shall be in accordance with above sequence in

case of power ON/OFF.

(NOTE 2) Before DISP rise up, the signals of YD,LP,XCK,DATA and M must be input, and the above condition of

“a” must be satisfied. The signals which comply with the interface timing in Fig.5,Fig.6, and table 8,

must be input.

POWER ON

Symbol

Allowable value

a

0 ms MIN.

1 s MAX.

b

－

100 ns MAX.

c

50 ms MIN.

-

d

-

10 ms MAX.

POWER OFF

Symbol

Allowable value

ｅ

0 ms MIN.

1 s MAX.

ｆ

0 ms MIN.

1 s MAX.

ｇ

15 ms MIN.

－