DS3105 datasheet(75/110 Pages) MAXIM

75 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

75 of 110

OCR2

Output Configuration Register 2

61h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

OFREQ3[3:0]

Default

see below

Bits 3 to 0: Output Frequency of OC3 (OFREQ3[3:0]).

This field specifies the frequency of output clock OC3.

The frequencies of the T0 APLL and T4 APLL are configured in the T0CR1 and T4CR1 registers. The Digital1 and

Digital2 frequencies are configured in the MCR7 register. See section 7.8.2.3. The default frequency is set by the

O3F[2:0] bits, see Table 7-18. The decode of this field is controlled by the value of the OCR5.AOF3 bit.

AOF3=0: (standard decodes)

0000 = Output disabled (i.e. low)

0001 = 2 kHz

0010 = 8 kHz

0011 = Digital2 (see Table 7-8)

0100 = Digital1 (see Table 7-7)

0101 = T0 APLL frequency divided by 48

0110 = T0 APLL frequency divided by 16

0111 = T0 APLL frequency divided by 12

1000 = T0 APLL frequency divided by 8

1001 = T0 APLL frequency divided by 6

1010 = T0 APLL frequency divided by 4

1011 = T4 APLL frequency divided by 64

1100 = T4 APLL frequency divided by 48

1101 = T4 APLL frequency divided by 16

1110 = T4 APLL frequency divided by 8

1111 = T4 APLL frequency divided by 4

AOF3=1: (alternate decodes)

0000 = Output disabled (i.e. low)

0001 = T0 APLL frequency divided by 64

0010 = T4 APLL frequency divided by 20

0011 = T4 APLL frequency divided by 12

0100 = T4 APLL frequency divided by 10

0101 = T4 APLL frequency divided by 5

0110 = T4 APLL frequency divided by 2

0111 = T4 selected reference (after dividing)

1000 to 1111 = undefined

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