DS3105 datasheet(13/110 Pages) MAXIM

13 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

13 of 110

Table 6-4. SPI Bus Mode Pin Descriptions

See section 7.10 for functional description and section 10.4 for timing specifications.

Pin Name

(1)

Type

(2)

Pin Description

IPU

Chip Select

This pin must be asserted (low) to read or write internal registers.

SCLK

Serial Clock

SCLK is always driven by the SPI bus master.

SDI

Serial Data Input.

The SPI bus master transmits data to the device on this pin.

SDO

Serial Data Output.

The device transmits data to the SPI bus master on this pin.

CPHA

Clock Phase

See Figure 7-4.

0 = data is latched on the leading edge of the SCLK pulse

1 = data is latched on the trailing edge of the SCLK pulse

Table 6-5. JTAG Interface Pin Descriptions

See section 9 for functional description and section 10.5 for timing specifications.

Pin Name

(1)

Type

(2)

Pin Description

JTRST

IPU

JTAG Test Reset (active low).

Asynchronously resets the test access port (TAP) controller. If not used,

JTRST can be held low

or high.

JTCLK

JTAG Clock,

Shifts data into JTDI on the rising edge and out of JTDO on the falling edge. If not used, JTCLK

can be held low or high.

JTDI

IPU

JTAG Test Data Input.

Test instructions and data are clocked in on this pin on the rising edge of JTCLK. If not used,

JTDI can be held low or high.

JTDO

JTAG Test Data Output.

Test instructions and data are clocked out on this pin on the falling edge of JTCLK. If not used,

leave floating.

JTMS

IPU

JTAG Test Mode Select

Sampled on the rising edge of JTCLK and is used to place the port into the various defined

IEEE 1149.1 states. If not used connect to VDDIO or leave floating.

Table 6-6. Power Supply Pin Descriptions

Pin Name

(1)

Type

(2)

Pin Description

VDD

Core Power Supply.

1.8V

±10%.

VDDIO

I/O Power Supply.

3.3V

±5%.

VSS

Ground Reference .

AVDD_DL

Power Supply for OC6 Digital Logic.

1.8V

±10%.

AVSS_DL

Return for OC6 Digital Logic.

VDD_OC6

Power Supply for Differential Output OC6POS/NEG.

1.8V

±10%.

VSS_OC6

Return for LVDS Differential Output OC6POS/NEG.

AVDD_PLL1

Power Supply for Master Clock Generator APLL.

1.8V

±10%.

AVSS_PLL1

Return for Master Clock Generator APLL.

AVDD_PLL2

Power Supply for T0 APLL.

1.8V

±10%.

AVSS_PLL2

Return for T0 APLL.

AVDD_PLL3

Power Supply for T4 APLL.

1.8V

±10%.

AVSS_PLL3

Return for T4 APLL.

AVDD_PLL4

Power Supply for T0 APLL2.

1.8V

±10%.

AVSS_PLL4

Return for T0 APLL2.

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