DS3105 datasheet(49/110 Pages) MAXIM

49 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

49 of 110

TEST1

Test Register 1 (Not Normally Used)

03h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

PALARM

D180

—

8KPOL

Default

Bit 7: Phase Alarm (PALARM).

This real-time status bit indicates the state of the T0 DPLL phase lock detector.

See section 7.7.6. (NOTE: This is not the same as T0STATE=Locked.)

0 = T0 DPLL phase-lock parameters are met (FLEN, CLEN, NALOL, FLLOL)

1 = T0 DPLL loss of phase lock

Bit 6: Disable 180 (D180).

When locking to a new reference, the T0 DPLL first tries nearest-edge locking (

±180°)

for the first two seconds. If unsuccessful it then tries full phase/frequency locking (

±360°). Disabling the nearest-

edge locking can reduce lock time by up to two seconds but may cause an unnecessary phase shift (up to 360

°)

when the new reference is close in frequency/phase to the old reference. See section 7.7.5.

0 = normal operation: try nearest-edge locking then phase/frequency locking

1 = phase/frequency locking only

Bit 4: Resync Analog Dividers (RA).

When this bit is set the analog output dividers are always synchronized to

ensure that low-frequency outputs are in sync with the higher-frequency clock from the DPLL.

0 = synchronized for the first two seconds after power-up

1 = always synchronized

Bit 3:

Leave set to zero (test control).

Bit 2: 8kHz Edge Polarity (8KPOL).

Specifies the input clock edge to lock to on the selected reference when it is

configured for LOCK8K mode. See section 7.4.2.

0 = Falling edge

1 = Rising edge

Bit 1:

Leave set to zero (test control).

Bit 0:

Leave set to zero (test control).

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