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FT2232D Datasheet(PDF) 44 Page - Future Technology Devices International Ltd. |
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FT2232D Datasheet(HTML) 44 Page - Future Technology Devices International Ltd. |
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44 / 56 page ![]() DS2232D Version 0.91 © Future Technology Devices International Ltd. 2006 Page of 51 FT2232D Dual USB UART / FIFO I.C. Figure 29 - MCU Host Bus Emulation Mode Signal Timing - Write Cycle OSC A15..A8 AD7..0 ALE CS# WR# High Address Low Address Data t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 IORDY Time Description t1 High address byte is placed on the bus if the extended write is used. t2 Low address byte is put out. t3 1 clock period for address is set up. t4 ALE goes high to enable latch. This will extend to 2 clocks wide if IORDY is low. t5 ALE goes low to latch address and CS# is set active low. t6 Data driven onto the bus. t7 1 clock period for data setup. t8 WR# is driven active low. This will extend to 6 clocks wide if IORDY is low. t9 WR# is driven inactive high. t10 CS# is driven inactive, 1/2 a clock period after WR# goes inactive t11 Data is held until this point, and may now change |
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