FT2232D datasheet(45/56 Pages) FTDI

45 / 56 page

DS2232D Version 0.91

FT2232D Dual USB UART / FIFO I.C.

Figure 30 - MCU Host Bus Emulation Mode Signal Timing - Read Cycle

OSC

A15..A8

AD7..0

ALE

CS#

RD#

High Address

Low Address

t8 t9

IORDY

Hi-Z

Time

Description

High address byte is placed on the bus if the extended read is used - otherwise t1 will not occur.

Low address byte is put out.

1 clock period for address set up.

ALE goes high to enable address latch. This will extend to 2 clocks wide if IORDY is low.

ALE goes low to latch address, and CS# is set active low. This will extend to 3 clocks if IORDY is sampled

low. CS# will always drop 1 clock after ALE has gone high no matter the state of IORDY.

Data is set as input (Hi-Z), and RD# is driven active low.

1 clock period for data setup. This will extend to 5 clocks wide if IORDY# is sampled low.

RD# is driven inactive high.

CS# is driven inactive 1/2 a clock period after RD# goes inactive, and the data bus is set back to output.

Figure 31 - MCU Host Bus Emulation Mode Signal Timing - Clock (OSC) Signal

OSC

thigh

tlow

tperiod

Time

Description

Minimum

Typical Value

Maximum

Unit

tperiod

Clock Period

41.6

83.3

125.0

thigh

Clock signal high time

20.8

41.6

62.5

tlow

Clock signal low time

20.8

41.6

62.5

FT2232D Datasheet(PDF) 45 Page - Future Technology Devices International Ltd.

FT2232D Datasheet(HTML) 45 Page - Future Technology Devices International Ltd.

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