MA732 – 14-BIT, DIGITAL ANGLE SENSOR WITH ABZ & PWM OUTPUTS

MA732 Rev. 1.1

MonolithicPower.com

11

8/8/2022

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Figure 7: SPI Timing Diagram

Figure 8: Minimum Idle Time

Table 3: SPI Timing

Parameter (6)

Description

Min

Max

Unit

tidleAngle

Idle time between two subsequent angle transmissions.

150

ns

tidleReg

Idle time before and after a register readout.

750

ns

tnvm

Idle time between a write command and a register readout

(delay necessary for non-volatile memory updates).

20

ms

tcsL

Time between CS falling edge and SCLK falling edge.

80

ns

tsclk

SCLK period.

40

ns

tsclkL

Low level of SCLK signal.

20

ns

tsclkH

High level of SCLK signal.

20

ns

tcsH

Time between SCLK rising edge and CS rising edge.

25

ns

tMISO

SCLK setting edge to data output valid.

15

ns

tMOSI

Data input valid to SCLK reading edge.

15

ns

Note:

6) All values are guaranteed by design.

X

hi-Z

MSB

MSB

LSB

hi-Z

CS

SCLK

MOSI

MISO

LSB

t

idleAngle

t

idleReg

t

nvm

t

csL

t

sclk

t

MISO

t

MOSI

t

sclkL

t

sclkH

t

csH

t

MISO

t

MISO

MSB

MSB

X

CS

MISO

MOSI

t

idleAngle

Angle

Angle

Angle

Reg Value

Read Reg Cmd

t

idleReg

t

nvm

Angle

Angle

Angle

Write Reg Cmd

0

0

0

0

0

Reg Value

0

t

idleReg

Angle

t

idleReg

0

t

idleAngle

t

idleAngle

t

idleAngle