AD52070 datasheet(5/33 Pages) ESMT

5 / 33 page

ESMT

AD52070

Elite Semiconductor Microelectronics Technology Inc.

Publication Date: Oct. 2021

Revision: 1.1

5/33

Ordering Information

Product ID

Package

Packing

Comments

AD52070-QG28NRR

E-TSSOP 28L

2500 Units / Reel

1 Reels / Small Box

Green

Available Package

Package Type

Device No.

JA(℃/W)

JT(℃/W)

Exposed Thermal Pad

E-TSSOP 28L

AD52070

27.1

1.33

Yes (Note 1)

Note 1.1:

The thermal pad is located at the bottom of the package. To optimize thermal

performance, soldering the thermal pad to the PCB

’s ground plane is necessary.

Note 1.2:

JA is simulated on a room temperature (TA=25℃), natural convection environment test

board, which is constructed with a thermally efficient, 4-layers PCB (2S2P). The

measurement is simulated using the JEDEC51-5 thermal measurement standard.

Note 1.3:

JT represents the thermal resistance for the heat flow between the chip junction and the

package

’s top surface. It’s extracted from the simulation data with obtaining a cold

plate on the package top.

Note 1.4:

JT represents the thermal parameter for the heat flow between the chip junction

and the package

’s top surface center. It’s extracted from the simulation data for

obtaining

JA, using a procedure described in JESD51-5.

AD52070 Datasheet(PDF) 5 Page - Elite Semiconductor Memory Technology Inc.

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