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AD82178 Datasheet(PDF) 40 Page - Elite Semiconductor Memory Technology Inc. |
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AD82178 Datasheet(HTML) 40 Page - Elite Semiconductor Memory Technology Inc. |
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40 / 90 page ![]() ESMT AD82178 Elite Semiconductor Microelectronics Technology Inc. Publication Date: Jul. 2024 Revision: 1.3 40/90 Address 0X0D, 0X0E ,0X0F,0X10,0X11,0X12, 0X13,0X14 : Channel configuration registers AD82178 can configure each channel to enable or bypass DRC and channel volume and select the limiter set. Address 0X0D and 0X0E; where x=1 or 2 BIT NAME DESCRIPTION VALUE FUNCTION B[7:6] CxDRCGS Channel X DRC gain step 00 DRC gain step =0.5dB 01 DRC gain step =0.25dB 1x DRC gain step =0.125dB B[3] CxPCBP Channel x Power Clipping bypass 0 Channel x PC enable 1 Channel x PC bypass B[2] CxDRCBP Channel x DRC bypass 0 Channel x DRC enable 1 Channel x DRC bypass B[1] Reserved B[0] CxVBP Channel x Volume bypass 0 Channel x ’s master volume operation 1 Channel x ’s master volume bypass Address 0X0F, 0X10, 0X11, and 0X12; where x=3, 4, 5, 6 BIT NAME DESCRIPTION VALUE FUNCTION B[7:6] CxDRCGS Channel X DRC gain step 00 DRC gain step =0.5dB 01 DRC gain step =0.25dB 1x DRC gain step =0.125dB B[2] CxDRCBP Channel x DRC bypass 0 Channel x DRC enable 1 Channel x DRC bypass B[1] Reserved B[0] CxVBP Channel x Volume bypass 0 Channel x's master volume operation 1 Channel x ’s master volume bypass |
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