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PM4541 Datasheet(PDF) 12 Page - PMC-Sierra, Inc |
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PM4541 Datasheet(HTML) 12 Page - PMC-Sierra, Inc |
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12 / 46 page ![]() TELECOM STANDARD PRODUCT PMC-Sierra, Inc. PM4541 T1XC-EVBD PMC-920314 ISSUE 2 T1XC EVALUATION DAUGHTERBOARD 9 C4MB O J29-9 Inverted C4M clock. C16M O J29-10 Direct access to 16.388 MHz clock driving the MT8940. This pin is mainly provided for direct oscillator access. If the MT8940 is not used the 16.388 MHz clock can be replaced by a 2.048 MHz clock with access to the clock signal provided by this pin. C12M O J29-11 Direct access to 12.355 MHz clock driving the MT8940. This pin is mainly provided for direct oscillator access. If the MT8940 is not used the 12.355 MHz clock can be replaced by a 1.544 MHz clock with access to the clock signal provided by this pin. GND G J29-12 MT8940 DPLL header ground reference. 3.2.3 T1XC Headers A number of headers are provided which give direct access to the main functional pins on the T1XCs. Both devices on the daughterboard have the same pins brought out to headers and every effort has been made to insure that all headers are symmetrical with both devices. The T1XCs are uniquely identified by an east/west designation. The following table gives a brief description of the T1XC signals. For a more detailed description of the T1XC device, refer to the T1XC datasheet. Signal Type Ref (E) Ref (W) Description TAP O J9-1 J10-1 Transmit Analog Positive Pulse TAN O J9-2 J10-2 Transmit Analog Negative Pulse RAS I J9-3 J10-3 Receive Analog Signal REF I/O J9-4 J10-4 Receive Reference GND G J9-5 J10-5 T1XC Analog Ground Reference TCLKI I J15-1 J16-1 Transmit Clock Input TCLKO O J15-2 J16-2 Transmit Clock Output TDP/TDD O J15-3 J16-3 Transmit Digital Positive Line Pulse/ Transmit Digital DS-1 Signal TDN/TFLG O J15-4 J16-4 Transmit Digital Negative Line Pulse/ Transmit FIFO Flag TDLCLK/ TDLUDR O J15-5 J16-5 Transmit Data Link Clock/ Transmit Data Link Underrun TDLSIG/ TDLINT I/O J15-6 J16-6 Transmit Data Link Signal/ Transmit Data Link Interrupt |
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