PM5366-PI datasheet(196/267 Pages) PMC

196 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

184

A17

A18

A19

A20

A21

A22

A23

A24

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

M10

D10

D11

D12

M11

D13

D14

D15

D16

D17

D18

D19

D20

M12

D21

D22

D23

D24

T1 tributary asynchronous timing is compensated via the V3 octet. T1 tributary

link rate adjustments are optionally passed across the SBI via the V4. T1

tributary alarm conditions are optionally passed across the SBI bus via the link

rate octet in the V4 location.

In synchronous mode, the T1 tributary mapping is fixed to that shown in Table 27

and rate justifications are not possible using the V3 octet. The clock rate

information within the link rate octet in the V4 location is not used in synchronous

mode.

E1 Tributary Mapping

Table 29 shows the format for mapping 63 E1s within the SPE octets. The

timeslots and framing bits within each E1 are easily located within this mapping

for SONET/SDH byte synchronously mapped E1 applications. Unframed E1s

use the exact same format for mapping 63 E1s into the SBI except that the E1

tributaries need not align with the timeslot locations associated with channelized

E1 applications. The V1,V2 and V4 octets are not used to carry E1 data and are

either reserved or used for control information across the interface. When

enabled, the V4 octet carries clock phase information across the SBI. The V1

and V2 octets are unused and should be ignored by devices listening to the SBI

bus. The V5 and R octets do not carry any information and are fixed to a zero

value. The V3 octet carries an E1 data octet but only during rate adjustments as

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