PM5366-PI datasheet(233/267 Pages) PMC

233 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

221

Figure 61 illustrates the operation of the SBI ADD Bus, using positive and

negative justification requests as an example. (The responses to the justification

requests would take effect during the next multi-frame.) The negative

justification request occurs on the DS-3#3 tributary when SAJUST_REQ is

asserted high during the H3 octet. The positive justification occurs on the DS-3#2

tributary when SAJUST_REQ is asserted high during the first DS-3#2 octet after

the H3 octet.

13.7.1 Notes on 77.76 MHz SBI Bus Operation

SBI bus operation at 77.76MHz is simply a byte interleaved multiplex of a 19.44

MByte/s stream with idle cycles. The STM-1 of interest is identified by the

LSTM[1:0] bits of the Master Bus Configuration register. On the Add bus, the

three unused STM-1s are simply ignored, including parity. On the Drop bus, the

unused STM-1s are high-impedance. The following is of special note:

1. Regardless of the state of the SSTM[1:0] bits, the SAC1FP and SDC1FP

pulses always identify the first byte of the frame.

2. Up to four devices may be directly connected to the same bus. Current

consumption is minimized if all devices are the same (ie. all TEMAP-84s).

All devices must receive the same SAC1FP and SDC1FP signals.

3. The Telecom bus becomes unconditionally high-impedance upon either a

hardware or software reset. All necessary configuration and at least one

SDC1FP pulse should precede the setting of the GSOE register bit.

PM5366-PI Datasheet(PDF) 233 Page - PMC-Sierra, Inc